WEBVTT 00:00.000 --> 00:10.000 Yeah, I think I can start now. 00:10.000 --> 00:16.000 Hi, I'm E-min, and I'll be talking about open source 00:16.000 --> 00:19.000 two trends for things that I'm in as a system today. 00:19.000 --> 00:24.000 First of all, myself, I'm a PhD student and I'm a amateur 00:24.000 --> 00:27.000 FPG programmer. I'm doing things like risk file and the 00:27.000 --> 00:30.000 design and also like things and attending microfares. 00:30.000 --> 00:33.000 These are some boards of view, I've built. 00:33.000 --> 00:37.000 There are the 8936XSDR for the pig set one board. 00:37.000 --> 00:41.000 I've talked about it on the first time 2020 online. 00:41.000 --> 00:43.000 I've also built boards like this. 00:43.000 --> 00:45.000 Eight layers, the U15EG. 00:45.000 --> 00:47.000 A well, it's still being debugged right now. 00:47.000 --> 00:52.000 There are also some other things and I've added support for 00:52.000 --> 00:58.000 a no-AMAMU Linux for 32-bit risk-5, but it's kind of something else. 00:58.000 --> 01:03.000 So I think our first start from ordinary open source FPGA 01:03.000 --> 01:07.000 two trends is relatively a new thing. 01:07.000 --> 01:12.000 The first support was came in 2015, which is project 01:12.000 --> 01:16.000 I-storm, is for the ethics as the 40 series, 01:16.000 --> 01:19.000 like in this board showing here. 01:19.000 --> 01:24.000 Largerist FPGA in this family is the I-C-40HSATK. 01:24.000 --> 01:27.000 It has 8,000 element logic elements. 01:27.000 --> 01:31.000 Then during the years, there can project failures for the 01:31.000 --> 01:35.000 Latest ECP-5 series and there are quite large ships and ships 01:35.000 --> 01:37.000 with transceivers. 01:37.000 --> 01:40.000 Recently, there are project arpecula for 01:40.000 --> 01:43.000 GoVFUGS. It's kind of a low-cost board. 01:43.000 --> 01:48.000 You may know the GoVin terminal is quite cheap and easy to use with this 01:48.000 --> 01:53.000 function, and for the maybe most widely used FPGA series, 01:53.000 --> 01:58.000 the AMD or Zelling 7 series, there is a single flow and then 01:58.000 --> 02:02.000 it's renamed to F4PGA, and it supports like 02:02.000 --> 02:09.000 RTX chips up to 200,000 of logic elements, which is already quite a lot. 02:09.000 --> 02:13.000 And now around two or three years ago, 02:13.000 --> 02:16.000 there can open actually 7. 02:16.000 --> 02:20.000 It's also for the 7 series FPGA, but it supports 02:20.000 --> 02:24.000 like most ships like a Spartan. 02:24.000 --> 02:28.000 There are RTX and also Kingtex, like shown here. 02:28.000 --> 02:33.000 Well, maybe a reason that Kingtex support came is, 02:33.000 --> 02:37.000 at that time there is a very cheap Kingtex board being released. 02:37.000 --> 02:43.000 This QMTack, Kingtex 7, a 325T. 02:43.000 --> 02:46.000 This cheap requires a Zelling license. 02:46.000 --> 02:50.000 It's not free, so maybe many people's thoughts 02:50.000 --> 02:53.000 or we'll just do the two-chain for this, and it came. 02:53.000 --> 02:56.000 And now we can use Kingtex FPGA series, 02:56.000 --> 02:58.000 which is open source purchase. 02:58.000 --> 03:01.000 So, no, no, we'll add only open source months. 03:01.000 --> 03:07.000 And here are some projects that are supported by open access 03:07.000 --> 03:08.000 7 right now. 03:08.000 --> 03:10.000 The green text are already supported part, 03:10.000 --> 03:13.000 like the famous PICO RB32, and like King with 5, 03:13.000 --> 03:16.000 or my SOC, or recently there's Uber DDR3, 03:16.000 --> 03:20.000 the very nice open source DDR3 controller. 03:20.000 --> 03:24.000 Of course, SD card or FDIM ad drivers will just work, 03:24.000 --> 03:28.000 and about the prime teams or hard-easy blocks 03:28.000 --> 03:30.000 inside the FPGA, 03:30.000 --> 03:33.000 we can expect like KLL, clock modules, 03:33.000 --> 03:35.000 and MMCM's just work. 03:35.000 --> 03:38.000 The IOS 3D is on ordinary RL pins, just works, 03:38.000 --> 03:42.000 and block RAM will also work. 03:42.000 --> 03:47.000 And the IO bank, both 3.3 volt and 1.8 volt IO will work. 03:47.000 --> 03:51.000 And now like, accept vertex, 03:51.000 --> 03:55.000 or Delling 7 series, cheap source supported, 03:55.000 --> 03:58.000 and the Zing 7 series program, 03:58.000 --> 04:00.000 will launch across the supported. 04:00.000 --> 04:03.000 The yellow text are projects that are being worked on, 04:03.000 --> 04:07.000 but it haven't come to a full support yet. 04:07.000 --> 04:10.000 It's mostly about like high speed transceivers. 04:10.000 --> 04:12.000 They are cellular controller being worked on. 04:12.000 --> 04:15.000 They are thinking about if the net being worked on, 04:15.000 --> 04:19.000 and they are using the GTP and GTX transceivers. 04:19.000 --> 04:24.000 And also there are PCI hot blocks in high end dynamics FPGA, 04:24.000 --> 04:27.000 and recently I'm also working on like, 04:27.000 --> 04:29.000 the support for the PCI hot block. 04:29.000 --> 04:31.000 So if it's lucky after a few months, 04:31.000 --> 04:34.000 maybe it will work as well, but particularly, 04:34.000 --> 04:37.000 since it's an open source, 04:37.000 --> 04:40.000 software can use it whatever ways we want. 04:40.000 --> 04:42.000 Like, ordinary VW, 04:42.000 --> 04:48.000 we only run on Windows and Linux on X6886 machines. 04:48.000 --> 04:52.000 But this one can run on arm machines like this M1 laptop, 04:52.000 --> 04:54.000 and we can also dockrize it, 04:54.000 --> 04:57.000 so users don't need to install them locally. 04:57.000 --> 05:01.000 Like, here are some of open source proteins stockrized, 05:01.000 --> 05:05.000 so you can just pull this one and start developing right now. 05:05.000 --> 05:08.000 And we can even use this for online services, 05:08.000 --> 05:09.000 because why not? 05:09.000 --> 05:10.000 There's no restrictions, 05:10.000 --> 05:15.000 and the size of the two chain is not so small, 05:15.000 --> 05:17.000 but also not so large. 05:17.000 --> 05:20.000 The open axis 7 may be a 5-6 GB, 05:20.000 --> 05:23.000 it's not that bad. 05:23.000 --> 05:26.000 And now, how about zinc? 05:26.000 --> 05:32.000 Well, things are complex devices with this kind of unique processing system 05:32.000 --> 05:34.000 plus programmable logic structure. 05:34.000 --> 05:37.000 The processing system, or PS, 05:37.000 --> 05:41.000 is actually a dual core arm processor. 05:41.000 --> 05:44.000 It has on DDR3 connected to it. 05:44.000 --> 05:46.000 There are ordinary arm peripherals like, 05:46.000 --> 05:48.000 it's a net in USB, 05:48.000 --> 05:50.000 and it's interesting like, 05:50.000 --> 05:54.000 the pins for those kind of high-speed peripherals 05:54.000 --> 05:56.000 can also be customized. 05:56.000 --> 06:00.000 It usually runs on runs, Linux, or autos. 06:00.000 --> 06:02.000 And on the FPG inside, 06:02.000 --> 06:06.000 it's a standard 7 series FPG fabric, 06:06.000 --> 06:10.000 but since there are not so many pins available, 06:10.000 --> 06:15.000 having DDR3 on these low-end things are not so popular, 06:15.000 --> 06:18.000 but we can still use it to do whatever thing we can with FPG, 06:18.000 --> 06:22.000 like, draw some HDMI or another Ethernet file, 06:22.000 --> 06:24.000 or like LEDs or buttons, 06:24.000 --> 06:26.000 and then we can also put custom logic, 06:26.000 --> 06:30.000 like a co-processor or accelerator to this PR part. 06:30.000 --> 06:36.000 So it can connect with the PS, with the high-speed interfaces 06:36.000 --> 06:40.000 in the between their axis and the GPIOs. 06:40.000 --> 06:44.000 And the thing is to start this device up, 06:44.000 --> 06:48.000 this can only be done from the PS part. 06:48.000 --> 06:51.000 So unlike ordinary FPG, 06:51.000 --> 06:54.000 we just have a flash attached to it, 06:54.000 --> 06:56.000 and it can start from the B-stream. 06:56.000 --> 06:59.000 Here we need the arm part to start up, 06:59.000 --> 07:02.000 and load the FPG as content, 07:02.000 --> 07:04.000 and set up, for example, 07:04.000 --> 07:07.000 clocks going from PS to the PL. 07:08.000 --> 07:10.000 Well, now there's a question that, 07:10.000 --> 07:15.000 are you confident building a thing put from our bioself? 07:15.000 --> 07:18.000 One, two, three, five, maybe? 07:18.000 --> 07:21.000 Well, my answer is actually no. 07:21.000 --> 07:23.000 Yeah, and if the answer is yes, 07:23.000 --> 07:25.000 then the question is how long does it take? 07:25.000 --> 07:28.000 Well, traditionally we'll be using this, 07:28.000 --> 07:31.000 the Vado flow, we'll begin from Vado. 07:31.000 --> 07:36.000 We'll use the block design to design our FPG fabric, 07:36.000 --> 07:40.000 and on the block design, there will be a special, 07:40.000 --> 07:43.000 like IP call called the GPS, 07:43.000 --> 07:46.000 and when we double click this, 07:46.000 --> 07:47.000 we will see this interface, 07:47.000 --> 07:50.000 and we will configure all our arm parameters, 07:50.000 --> 07:51.000 like the DDR3 parameters, 07:51.000 --> 07:53.000 like what IO pins we are using, 07:53.000 --> 07:56.000 like the PSPR interconnect, 07:56.000 --> 07:57.000 right down here. 07:57.000 --> 07:59.000 This may bring an illusion 07:59.000 --> 08:02.000 that this information are stored in the B-stream, 08:02.000 --> 08:05.000 but actually it's not the case. 08:05.000 --> 08:08.000 It's totally separated, and for example, you can try, 08:08.000 --> 08:11.000 like setting, changing some parameters, 08:11.000 --> 08:12.000 and generally the B-stream again, 08:12.000 --> 08:15.000 you'll find the B-stream is exactly the same. 08:15.000 --> 08:19.000 And actually this is a start externally, 08:19.000 --> 08:21.000 like when we export hardware from Vado, 08:21.000 --> 08:23.000 this board package will be generated. 08:23.000 --> 08:25.000 It will contain the B-stream, 08:25.000 --> 08:28.000 and the PS in it does see is 08:28.000 --> 08:31.000 the register rise to bring up the arm core, 08:31.000 --> 08:35.000 and a small export hardware storage is 08:35.000 --> 08:40.000 more like a minimum configuration for software. 08:40.000 --> 08:44.000 And then we will export this to Zarynx SDK, 08:44.000 --> 08:48.000 and in the SDK we will build the first stage bootloader 08:48.000 --> 08:49.000 or FSPL, 08:49.000 --> 08:53.000 and like your user app running on the uncourse. 08:53.000 --> 08:56.000 Like for Linux, this user app will be your boot, 08:56.000 --> 08:58.000 but here I'm just talking about the most simple case. 08:59.000 --> 09:01.000 And then after this, the bootloader 09:01.000 --> 09:05.000 can be generated and put down to your boot device. 09:10.000 --> 09:13.000 Well, all of these flows can be automated, 09:13.000 --> 09:16.000 like for Vado, there are TCL scripts, 09:16.000 --> 09:18.000 but for most use cases, 09:18.000 --> 09:21.000 it's still a flow heavily based on, 09:21.000 --> 09:23.000 like GUI and most clicks, 09:23.000 --> 09:25.000 there are maybe hundreds of most clicks, 09:25.000 --> 09:28.000 and it cannot be done in a very short time. 09:28.000 --> 09:31.000 But now we have an open source version, 09:31.000 --> 09:34.000 the Open Access 7 plus the new Gen Z. 09:34.000 --> 09:38.000 And with this flow, we can build this bootloader 09:38.000 --> 09:40.000 in less than five minutes. 09:40.000 --> 09:43.000 Like here, the PL configuration, 09:43.000 --> 09:46.000 the B-stream and the PS configuration are separated, 09:46.000 --> 09:48.000 and this Gen Z is specially designed 09:48.000 --> 09:54.000 to generate this PSP files from a text based configuration. 09:55.000 --> 09:58.000 And then we use the open source settings 09:58.000 --> 10:01.000 in various software library and your ordinary switching 10:01.000 --> 10:03.000 to build the EF files. 10:03.000 --> 10:06.000 Then there can be a small tool called 10:06.000 --> 10:09.000 from a macro, is the tick-unkay boot image 10:09.000 --> 10:11.000 to generate this bootload bin. 10:11.000 --> 10:15.000 So it's all like text and online based flow. 10:15.000 --> 10:18.000 Like what Gen Z is actually doing 10:18.000 --> 10:21.000 is to set up all those registers 10:21.000 --> 10:23.000 to correctly bring up the ARM course. 10:23.000 --> 10:25.000 There are maybe hundreds of registered rights. 10:25.000 --> 10:29.000 And well, I would say it's simpler than reverse engineering 10:29.000 --> 10:30.000 the FUGA itself, 10:30.000 --> 10:34.000 because we have these technical reference manual available. 10:34.000 --> 10:36.000 As mostly those file files, 10:36.000 --> 10:38.000 there are PLLs, 10:38.000 --> 10:42.000 three of them for the ARM course and then DDR 10:42.000 --> 10:44.000 and then the IO peripherals. 10:44.000 --> 10:46.000 And then these PLLs will be used 10:46.000 --> 10:49.000 to derive all the clock frequencies. 10:49.000 --> 10:51.000 There are also DDR, 10:51.000 --> 10:54.000 not the party ran out, it's been worked out. 10:54.000 --> 10:57.000 And there are pins on the PSI. 10:57.000 --> 11:01.000 It's interesting that the flexibility of the PSP 11:01.000 --> 11:06.000 is achieved by a custody layer of maxis. 11:06.000 --> 11:08.000 So like high speed peripherals, 11:08.000 --> 11:10.000 we'll go through only one layer of max. 11:10.000 --> 11:12.000 And the lowest speed peripherals 11:12.000 --> 11:14.000 will go through all those maxis. 11:14.000 --> 11:18.000 And there are peripherals like specific registers, 11:18.000 --> 11:20.000 the URs, border rate, or whatever. 11:20.000 --> 11:21.000 And there are some debug entries, 11:21.000 --> 11:24.000 which maybe no one knows what they are doing. 11:24.000 --> 11:26.000 And I can demonstrate the brand now. 11:35.000 --> 11:36.000 Sorry. 11:40.000 --> 11:44.000 So here is already a gen Z crown here, 11:44.000 --> 11:47.000 and the open access 7 is in Docker containers. 11:48.000 --> 11:52.000 I have modified this slightly for this ARM machine. 12:00.000 --> 12:04.000 So we will use this, no DDR SD boot example. 12:04.000 --> 12:07.000 And that there's already me to read. 12:07.000 --> 12:11.000 And for the FPGA part, 12:11.000 --> 12:15.000 we have a very minimum PSP out configuration example 12:15.000 --> 12:18.000 in this FPGA. 12:18.000 --> 12:21.000 There is a minimum actually device, 12:21.000 --> 12:23.000 actually GPIO. 12:23.000 --> 12:29.000 And then there is this instantiation of this PS7 hard block. 12:29.000 --> 12:31.000 There are no parameters here, 12:31.000 --> 12:34.000 because our parameters are set by ARM. 12:34.000 --> 12:37.000 In FPGA, it's just like a placeholder. 12:37.000 --> 12:42.000 And we can just call this Dockerize the two chain. 12:46.000 --> 12:48.000 I'll run uses. 12:48.000 --> 12:52.000 And then next point in root. 12:56.000 --> 12:58.000 And then this print generation. 12:58.000 --> 13:01.000 So now the print print have been built. 13:01.000 --> 13:04.000 And we can prepare the PS part. 13:04.000 --> 13:07.000 I have cloned this embedded software library here. 13:07.000 --> 13:09.000 And we can first 13:09.000 --> 13:16.000 create a new folder in this PSP. 13:16.000 --> 13:21.000 And then we launch a gen Z to generate 13:21.000 --> 13:23.000 our specific PSP files. 13:23.000 --> 13:25.000 We'll just be using this file. 13:25.000 --> 13:29.000 On top of it is a huge array. 13:29.000 --> 13:32.000 It's kind of similar to the device configuration. 13:32.000 --> 13:35.000 But of course, this time we handled by text. 13:35.000 --> 13:37.000 The most entries are not used. 13:37.000 --> 13:40.000 And only some are selected. 13:40.000 --> 13:43.000 Like this UART. 13:43.000 --> 13:44.000 Like there's SD card, 13:44.000 --> 13:47.000 labeled by one here. 13:47.000 --> 13:50.000 And we'll specify like bought rate and frequency. 13:50.000 --> 13:54.000 And like bank voltages. 13:54.000 --> 13:56.000 And then we'll just run it. 13:56.000 --> 13:59.000 And you can see the PRL parameters are calculated. 13:59.000 --> 14:04.000 And the ML pins are set. 14:04.000 --> 14:06.000 And if you look at the file, we generated. 14:06.000 --> 14:09.000 We can see in this PRL server in it. 14:09.000 --> 14:15.000 There are quite a lot of values to write. 14:15.000 --> 14:20.000 And this xprimus.h contains some parameters like the arm frequency. 14:20.000 --> 14:27.000 I like what was the UART address. 14:27.000 --> 14:33.000 And then we can copy this generated file into this embedded software library. 14:33.000 --> 14:35.000 And then run the mix. 14:35.000 --> 14:40.000 This is FSBL. 14:40.000 --> 14:48.000 And then this is the hollow world. 14:48.000 --> 14:49.000 We can find those. 14:49.000 --> 14:51.000 Yeah, I've started generated. 14:51.000 --> 14:53.000 And now it's time to generate the puto bin. 14:53.000 --> 14:56.000 It is the same as on ZANX SDK. 14:56.000 --> 15:02.000 We'll use a small PR file to specify what's inside. 15:02.000 --> 15:09.000 So then generate using this empty puto bin. 15:09.000 --> 15:16.000 And here, we can see the puto bin already generated. 15:16.000 --> 15:31.000 We can then copy it to ask card connected here. 15:31.000 --> 15:34.000 This is the SD card and the file is there. 15:34.000 --> 15:42.000 Now I'll plug it into this thingboard. 15:42.000 --> 15:47.000 And they'll connect the power with my power bank. 15:47.000 --> 15:50.000 I hope it works. 15:50.000 --> 15:51.000 Yeah, it works. 15:51.000 --> 15:53.000 You can see this is the power LED. 15:53.000 --> 15:59.000 And those two blinking LED are driven by the arm force. 15:59.000 --> 16:00.000 Sending commands. 16:00.000 --> 16:02.000 They're the X interface. 16:02.000 --> 16:07.000 And then the XTG panel in the FUGA is blinking this LED. 16:07.000 --> 16:13.000 Thank you. 16:13.000 --> 16:15.000 No, thank you. 16:15.000 --> 16:16.000 I'll continue this. 16:16.000 --> 16:18.000 So now we have open source quotient. 16:18.000 --> 16:19.000 What does this mean? 16:19.000 --> 16:24.000 Well, maybe one interesting thing to look at is this RP2040. 16:24.000 --> 16:28.000 Which is famous as this Raspberry Pi pickle. 16:28.000 --> 16:31.000 I know it's far away from a fair comparison. 16:31.000 --> 16:35.000 But this RP2040 also has a similar structure. 16:35.000 --> 16:39.000 Like, it's PLS is a dual-core quotient zero. 16:39.000 --> 16:45.000 And the PLS is a six-programbo logic Iowa modules or PIO modules. 16:45.000 --> 16:50.000 And these are quite popular among the emters and developers. 16:50.000 --> 16:54.000 On the things side, of course, we have an ordinary thing. 16:54.000 --> 16:59.000 By the two-chain, the RP2040 has a standard open source quotient. 16:59.000 --> 17:02.000 You can just download this pickle as you can from GitHub. 17:02.000 --> 17:03.000 It's only two megabytes. 17:03.000 --> 17:05.000 It can run everywhere. 17:05.000 --> 17:10.000 But previously, on the outside, we have a very proprietary two-chain. 17:10.000 --> 17:12.000 It's maybe 20 gigabytes large. 17:12.000 --> 17:16.000 And we'll need to agree and fill out this government support approval. 17:16.000 --> 17:18.000 It's causing problems sometimes. 17:18.000 --> 17:21.000 But now with this open source quotient, 17:21.000 --> 17:24.000 it's as free as the RP2040, I would say. 17:24.000 --> 17:27.000 And we can just talk real cool and get long. 17:27.000 --> 17:31.000 And like I've showed this very easy to use. 17:31.000 --> 17:35.000 And the body hardware, things are complex hardware. 17:35.000 --> 17:38.000 But I think it's mostly about the two-chain. 17:38.000 --> 17:40.000 The two-chain is too hard to use. 17:40.000 --> 17:46.000 So maybe that's why not so many people are using it for beginners projects. 17:46.000 --> 17:48.000 There are quite some boards available. 17:48.000 --> 17:52.000 We have a trust electronics, Zinc Barabai Zero. 17:52.000 --> 17:54.000 There's this D41. 17:54.000 --> 17:56.000 It's also has no DDR. 17:56.000 --> 17:59.000 And this is the famous E-BAS 403. 17:59.000 --> 18:04.000 It's a up-cycle mining rigs controller board. 18:04.000 --> 18:07.000 So after the mining firm error have retired, 18:07.000 --> 18:09.000 this controller board came to market at a very low price. 18:09.000 --> 18:11.000 So maybe only 10 euro. 18:11.000 --> 18:12.000 And many amateurs have this. 18:12.000 --> 18:15.000 But previously, the two-chain is kind of very hard to use. 18:15.000 --> 18:18.000 So maybe that's why many people have it. 18:18.000 --> 18:22.000 But maybe there are a few people really use most of it. 18:22.000 --> 18:26.000 And the body in the middle is the one I've showed just now. 18:26.000 --> 18:28.000 And actually this PCB have only two layers. 18:28.000 --> 18:31.000 But still have this 400-pin BGA. 18:31.000 --> 18:35.000 It's very interesting that the signal integrity is very, very bad. 18:35.000 --> 18:39.000 But it can still drive a BGA and like, 18:39.000 --> 18:42.000 as to ram at over 100 negatives. 18:42.000 --> 18:45.000 So that's the hardware part. 18:45.000 --> 18:47.000 And about the software part actually, 18:47.000 --> 18:50.000 I found there are some interesting things to do. 18:50.000 --> 18:52.000 Like, when we are using the proprietary pushing, 18:52.000 --> 18:54.000 we will just like follow the instructions. 18:54.000 --> 18:58.000 And if they say this is impossible, maybe I'm going to try that. 18:58.000 --> 19:01.000 Like, the Zinc boot without DDR. 19:01.000 --> 19:03.000 I don't know how many people have done this. 19:03.000 --> 19:07.000 But the official document said it's only possible, 19:07.000 --> 19:09.000 like to boot from QRSPSF. 19:09.000 --> 19:15.000 Because by loading this train to the FPGA, 19:15.000 --> 19:20.000 we will need one single DDR mill request from like a certain memory, 19:20.000 --> 19:25.000 holding the hobby stream through this 0x AFF address. 19:25.000 --> 19:30.000 And if there's no DDR, then the single place we can map the whole 19:30.000 --> 19:34.000 this premium to memory is by execution in place by QRSPSF. 19:34.000 --> 19:38.000 But actually I found it's not really the case. 19:38.000 --> 19:41.000 And this DDR mill request can actually be divided into many, 19:41.000 --> 19:44.000 minus more part, like 20 kilobyte at a time. 19:44.000 --> 19:50.000 So by this way, we can just easily load this from SD card, 19:50.000 --> 19:54.000 using a very small amount of like buffer memory. 19:54.000 --> 19:59.000 So of course, on this board is also this case. 19:59.000 --> 20:03.000 The feature here is like another board is the similar thing. 20:03.000 --> 20:05.000 And it also has no DDR. 20:05.000 --> 20:09.000 And I can also demonstrate that if I plug in the power supply, 20:09.000 --> 20:12.000 the build stream can be loaded and it begins blinking. 20:12.000 --> 20:14.000 And the speed is really fast. 20:14.000 --> 20:16.000 It's many small segments. 20:16.000 --> 20:20.000 But there's not so much speed penalty. 20:20.000 --> 20:23.000 And also we can overclock the zinc core. 20:23.000 --> 20:26.000 Previously, it's done by in Libra, as the R. 20:26.000 --> 20:29.000 But manually passing this map ready to rise. 20:29.000 --> 20:32.000 But now in Gen Z, since these parameters are calculated from scratch, 20:33.000 --> 20:36.000 it's just a set in one parameter and you're done. 20:36.000 --> 20:39.000 So if you need some margin performance, it's very interesting to try. 20:39.000 --> 20:42.000 And well, we can have more flexibility. 20:42.000 --> 20:44.000 So like, there's a cool demo. 20:44.000 --> 20:46.000 I put it on the YouTube. 20:46.000 --> 20:50.000 That can be kind built a PRB stream on the zinc's arm core. 20:50.000 --> 20:53.000 Because the pushing is very software. 20:53.000 --> 20:56.000 It runs on arm and it requires maybe one gigabytes of memory. 20:56.000 --> 20:59.000 And on this pink Z1 is half a gigabytes of memory. 20:59.000 --> 21:01.000 And so I did half gigabytes of swap. 21:01.000 --> 21:04.000 It's kind of slow, but it works. 21:04.000 --> 21:09.000 And you can program the PR from the TS like on the fly. 21:09.000 --> 21:13.000 And previously, it's mostly about small zinc devices. 21:13.000 --> 21:18.000 And now, since the zinc is a kinesthetic, also supported. 21:18.000 --> 21:22.000 In principle, the broads like this will also be supported as well. 21:22.000 --> 21:25.000 So far, I only did blinking on this, but maybe in the future, 21:25.000 --> 21:28.000 there can be more interesting scenes happening. 21:29.000 --> 21:32.000 So about the future, I think it will be more free. 21:32.000 --> 21:36.000 We have STR devices, like PLOT STR and like Open Wi-Fi. 21:36.000 --> 21:39.000 There are STRs with zinc running in the satellites. 21:39.000 --> 21:44.000 And I think now, this from our compiled by STU withado. 21:44.000 --> 21:48.000 But in the future, I think maybe some of you are proud of this, 21:48.000 --> 21:49.000 to open source pushing. 21:49.000 --> 21:52.000 And we will have a more open infrastructure. 21:52.000 --> 21:55.000 And of course, the pedal index is kind of a tool 21:55.000 --> 21:58.000 for like a generator in the whole file system. 21:58.000 --> 22:01.000 But maybe it's not so easy to use. 22:01.000 --> 22:06.000 So it's also my plan to support this kind of generation. 22:06.000 --> 22:11.000 So to have open source tool to replace this pedal index. 22:11.000 --> 22:14.000 I finally, I would like to thank our net foundation and GIS zero. 22:14.000 --> 22:17.000 And for forming this project, I would also like to thank SIMBOT.DDA 22:17.000 --> 22:20.000 and the Open Compute project and OCP time applicant project. 22:20.000 --> 22:24.000 And also the next user group and VLAB in the University of San San Technology of China. 22:24.000 --> 22:26.000 So that's all of them. 22:26.000 --> 22:27.000 Thanks. 22:27.000 --> 22:30.000 Thank you very much. 22:36.000 --> 22:37.000 Did you have any questions? 22:37.000 --> 22:38.000 Yeah. 22:38.000 --> 22:39.000 Do we have any questions? 22:45.000 --> 22:52.000 Why didn't you use Open FPGA loader instead of a SD card 22:52.000 --> 22:59.000 you can refresh your FPGA with FTDI? 23:00.560 --> 23:04.520 I think the reason is, FPGA loader is used 23:04.520 --> 23:07.440 to program the FPGA from a computer, 23:07.440 --> 23:09.640 about to make it both from itself. 23:11.560 --> 23:15.600 The only way is to use open FPGA loader 23:15.600 --> 23:18.720 is to have a external MCU to beat down the jet height. 23:18.720 --> 23:20.200 So in this case, having an SD card 23:20.200 --> 23:23.200 is something like most traffic all the way, isn't it? 23:23.200 --> 23:26.560 There are some SD card features 23:26.560 --> 23:31.480 where you could say switch from this to this. 23:31.480 --> 23:32.680 This is used by Lava. 23:32.680 --> 23:36.600 So it would be a way to automate that. 23:36.600 --> 23:38.880 OK, thank you. 23:38.880 --> 23:40.720 The name is called this SD Marks. 23:40.720 --> 23:52.520 It's there in the gun to support the ZNKB or the ZNKB. 23:52.520 --> 23:57.920 Well, about ZNKMP, I believe the PS configuration 23:57.920 --> 24:03.120 might be doable, but since it's also stable and so far, 24:03.120 --> 24:05.280 as far as I know, there's no open source tool change 24:05.280 --> 24:07.120 for office-scale fabric here, 24:07.120 --> 24:09.840 so maybe you need to weigh some time. 24:09.840 --> 24:11.440 OK, thank you. 24:29.440 --> 24:33.520 As far as I know, we were to also include 24:33.520 --> 24:38.680 debunking tools like ILA, for example, for custom logic, 24:38.680 --> 24:46.920 and debunking custom hardware in the programming logic 24:46.920 --> 24:53.400 by connecting the Amphrocessor via special debunking 24:53.400 --> 24:57.640 world, so you can trigger an ILA for from the software 24:57.640 --> 25:06.560 in the program, program-able logic, sorry. 25:06.560 --> 25:13.400 Does do some open source tool exist to replace 25:13.400 --> 25:18.000 that component from the Vado? 25:18.000 --> 25:20.360 I'm sorry, but I haven't used a servicing 25:20.360 --> 25:23.760 and probably not because when we are using open source 25:23.760 --> 25:27.080 tool change, there will no longer be ILA. 25:27.080 --> 25:32.400 We will be able to like hook up some custom code and monitor. 25:32.400 --> 25:35.560 But since the tool change is being developed itself, 25:35.560 --> 25:38.680 if something went wrong, you don't know if it's the debugger or the design 25:38.680 --> 25:42.280 itself, so it is kind of complicated. 25:50.760 --> 25:51.760 Thank you. 25:51.760 --> 25:55.200 Thank you, unfortunately, year out of time for questions.