WEBVTT 00:00.000 --> 00:11.440 So our next presentation will be from Lottick-Grabinski. 00:11.440 --> 00:19.240 We have had a number of presentations on the various bits of hardware and the missing 00:19.240 --> 00:22.880 component is always the open PDK. 00:22.880 --> 00:29.880 We are going to hear now about how to fill in these gaps with the open PDK initiative. 00:29.880 --> 00:40.040 So please give a warm welcome to Lottick. 00:40.040 --> 00:42.760 Thank you very much for your introduction. 00:42.760 --> 00:53.160 I am really happy to join the forum and having you recognizing the importance of our open PDK 00:53.160 --> 00:54.880 initiative. 00:54.880 --> 01:00.880 I am standing here for IHP, IHP's R&D institution in Germany in Frankfurt on 01:00.880 --> 01:07.280 other, so it's a Polish German border, it's other Frankfurt, and they are very 01:07.280 --> 01:12.520 fair to join open PDK initiative. 01:12.520 --> 01:23.120 I will present the status that tools we are establishing for mainly analog RF design and at 01:23.120 --> 01:32.200 very end our vision of federal development following recently published Rautma. 01:32.200 --> 01:39.120 And what the Grabinski is my private direct email address, I am also managing Mosek 01:39.120 --> 01:47.360 K Association, which all organized serious of compact modeling, spy simulation workshop 01:47.440 --> 01:58.240 and very bottom, it's my direct email address at IHP when I am consulting for open PDK 01:58.240 --> 02:03.200 initiative supporting IHP team. 02:03.200 --> 02:09.200 This is outline and I will start with motivation. 02:09.200 --> 02:17.320 As you see this forum that's depleted and the issue or question about building 02:17.400 --> 02:24.200 talents and skills for our engineering domain, it's quite critical. 02:24.200 --> 02:32.840 I'm referring to quite old presentation by Joe DeBoc, the VP of IHMek. 02:32.840 --> 02:41.160 He was addressing this issue on different forums, including public hearing of European 02:41.240 --> 02:46.440 chip arcs in Strasbourg. 02:46.440 --> 02:53.240 It took European Commission about two years to come to this numbers. 02:53.240 --> 03:00.120 Our room is depleted, it's not only this room in our microchronics engineering domain, 03:00.120 --> 03:09.560 but as you see everything from designs, tests, software development in our semiconductor 03:10.120 --> 03:24.760 microchronics domain lacks huge number of technician engineers researchers that different 03:24.760 --> 03:33.960 reason for this, but we believe that open PDK in each out of its solution, it will help us 03:34.040 --> 03:41.640 to attract younger generation students, young engineers, researchers to our domain 03:41.640 --> 03:48.280 to support all what we are doing. We are not very first to face this issue. 03:48.280 --> 03:56.280 In India project a faulty project and each of them is a project 03:56.280 --> 04:03.400 are running for a couple of years. They are to my understanding what I remember, they were very 04:03.400 --> 04:12.200 first to use complete open source design flow to introduce maybe not-tingering engineers, 04:12.200 --> 04:18.520 but that young students and engineering to a mallectronic. They started with 04:18.520 --> 04:27.480 a simple second design using discreet components, they were simulating with engineers, 04:27.480 --> 04:36.680 engineers, what was introduced earlier and doing PCB boards with Kikat and what is important 04:36.680 --> 04:45.960 to highlight, they are not just introducing the tools, but they have huge library, they call this 04:45.960 --> 04:55.880 spoken tutorials where they address different topics of circuit design, modeling simulation, 04:55.880 --> 05:05.000 PCB design, moreover they translated to local languages also to other languages including 05:05.000 --> 05:11.240 European, I was surprised to see huge library of spoken tutorial in Portuguese. So just visit 05:11.240 --> 05:20.200 website and you will find really a lot of resources even for beginner to start joining our activities. 05:22.440 --> 05:29.400 Our friends with Google support in United States, they joined or they were very 05:29.400 --> 05:36.760 first to open pdk's and they managed to convince sky water and global funderate that two 05:36.760 --> 05:47.160 I see manufacturers in the United States offering not only open pdk, but they built complete 05:47.160 --> 05:56.360 open source design flow. China, they do not sleep, they have initiative one student one 05:56.360 --> 06:03.960 chip and they claim having something like 10,000 student doing designs, I wish I could have a 06:03.960 --> 06:11.960 fraction of my electronic student designing chips in Europe. The same applies to Japan, 06:13.320 --> 06:20.040 they follow concept of Google and Fabulous, but they are talking to domestic funders to join in 06:21.000 --> 06:33.720 IHP offers unique process it's bipolar with silicon germanium devices operating up to 450 06:33.720 --> 06:45.000 gigahertz on silicon germanium silicon germanium semiconductors this is unique it's about half a 06:45.080 --> 06:51.960 terahertz silicon devices there is a complete set of devices available for 06:53.560 --> 07:01.960 analog RF design for all who are within digital it's based on standard CMOS process 07:01.960 --> 07:09.400 little bit telegacy 130 but it's perfect for digital huge digital blocks prototyping. 07:10.120 --> 07:18.520 All what we are offering it's not open pdk it's not only design flow we have built but we also 07:20.360 --> 07:29.240 offering free multi-project waveforms so if you design your circuit in this flow you can submit 07:29.880 --> 07:39.640 this year we have four subsequent type out your submit your design will be validated 07:39.640 --> 07:48.200 sent for manufacturing at very end you will receive hopefully working piece of silicon chip for testing 07:49.160 --> 07:58.280 scan the QR code which points you to all information about submission 07:59.080 --> 08:02.600 precision so I will keep this slide for a while 08:08.200 --> 08:16.920 this is this is I like really high level abstract view on all what is available in pdk 08:18.200 --> 08:26.360 you learn about different components first column it's probably it does not turn is it 08:26.360 --> 08:33.880 part of open pdk but then passive components individual semiconductor devices 08:35.640 --> 08:45.160 digital cells a part of schematic view behind each device passive or active there is 08:45.240 --> 08:54.200 other representation for passive components we need 3D modeling so there is input to run 08:54.200 --> 09:02.440 electromagnetic simulation and going from schematic to real integrated spiral inductor in your chip 09:02.440 --> 09:12.360 the same applies to semiconductor devices most fed by polar or digital blocks or digital cells 09:12.440 --> 09:22.440 which has a very low pure very low digital representation and then having a layout you are 09:22.440 --> 09:33.800 submitting your chip for manufacturing this is not a part of open pdk but for all who are working 09:33.800 --> 09:41.640 at the device level trying to understand the physics I would recommend to go through 09:41.640 --> 09:51.720 ticard tools and we have huge selection this is just for example of 2D 3D modeling simulation 09:51.720 --> 09:59.640 tools cider is fully integrated with ngspice so virtually you can do numeric 09:59.640 --> 10:07.000 semiconductor device modeling and simulation without leaving ngspice and then build this 10:07.960 --> 10:14.760 numeric representation simulated device in your sub-circuit you can imagine having numeric 10:14.760 --> 10:25.880 alert presentation of your MOSFET device spice model you can build sub-circuit and simulate 10:25.880 --> 10:36.520 complete sub-circuit with ngspice digital flow it's well established we are using open route 10:36.520 --> 10:43.400 and to explain this slide probably I would need yet another presentation we are focusing on 10:43.400 --> 10:52.840 RF design this is what we brought together we have quacks and xm for schematic entry with ngspice 10:52.840 --> 11:04.360 and zi for transistor level simulation k layout on magic for layout gds to design the tools 11:04.440 --> 11:13.960 supporting design rule check physical validation this is like last week extension we have also 11:13.960 --> 11:22.440 parasitic extraction tool supporting k layout I was referring to numeric simulation we need to 11:22.440 --> 11:28.120 numeric assimilation for passive components interconnex transmission line integrated 11:28.440 --> 11:36.360 antenna spiral inductors which are part so we have two tools which are open source 11:36.360 --> 11:47.640 open ems and we have also elmer for these tasks always well defined and you can find even 11:48.360 --> 11:58.680 well prepared set of dockers with all the tools which I'm listing here you already know 11:58.680 --> 12:05.720 quacks it was presented a couple of times at first them also within this room I'm glad to see 12:05.720 --> 12:15.160 for the developers joining us here on each slide you have a reference to page where 12:15.240 --> 12:26.920 tool is available for download I already talked about numeric assimilation we need this to get 12:28.600 --> 12:35.720 spice or representation of spiral inductors it could be set of esparometers or lumped model 12:36.680 --> 12:45.800 passive component sub-circuit to represent quite complex in fact to the structure of spiral 12:45.800 --> 12:54.600 inductor which is part of an analog design compact model of very critical for 12:55.320 --> 13:07.960 open pdk and in particle spice libraries they are core of the pdk the quality of pdk 13:07.960 --> 13:15.160 quality of your design depends on the the model how it was extracted implemented 13:16.040 --> 13:24.760 having all statistical core of the models short distance matching for analog simulation 13:24.760 --> 13:35.640 the references explaining very log a code it's a game topic for yet another lecture this 13:35.640 --> 13:42.600 keyword was coming in and despite presentation no cover presentation we have outstanding very fast 13:42.680 --> 13:53.080 robots very log a compiler to bring new models to our pdk compact model verification validation 13:53.080 --> 13:59.720 is critical so I'm glad to my application to develop test precision for model 13:59.800 --> 14:04.360 validation was recognized and is supported by an neural net 14:06.360 --> 14:15.720 buff was briefly introduced I will skip this slide again there are references and 14:15.720 --> 14:26.200 Felix was talking about alternative tool which would allow very log amst complete model 14:26.280 --> 14:35.080 compilation kikat as we here in this room it's important tool because after designing 14:35.080 --> 14:40.760 geochip you have a piece of silicon eventually package and then you have to create the 14:40.760 --> 14:49.960 test board to validate and it's a former area presentation by holder he was talking about 14:50.600 --> 14:56.840 engine spice which runs in the background of kikat which allows you to validate your 14:56.840 --> 15:06.440 seconded boarder ever all what we do at IC level with quarks or xhem so engine spice or size 15:06.440 --> 15:13.400 are really core simulation tools for all what we are doing testing it's important 15:13.400 --> 15:23.400 I was presenting this 2018 it did not draw attention but others they went even feather 15:23.400 --> 15:33.000 and brought unique platform to introduce student to simo's second single transistor 15:33.720 --> 15:41.960 characterization measurement and simulation and there is this Mobius chip which we recommended for 15:42.040 --> 15:50.200 open pdk and eventually will be manufactured in the one of upcoming runs this are digital designs 15:50.840 --> 15:59.240 each individual design it's multi million even multi core risk farf implementation which has been 15:59.240 --> 16:08.040 submitted for open pdk multi project waferan and they are manufactured at iHP 16:08.680 --> 16:16.600 there are a lot of publications where you can learn about design procedures starting from high 16:16.600 --> 16:25.240 level abstract like cut definition going down to synthesis of your chip and creating integrated 16:25.240 --> 16:36.040 circuits analog design it's not fully automatic they are we have a partners which are 16:36.760 --> 16:47.480 joining our open pdk initiative and coming with the analog design automation tools similar to 16:47.480 --> 16:59.560 open route but for analog RF application. Mosaic it's one of possible frameworks to work on IC design 17:00.280 --> 17:06.920 our partners at sub one university they have the color coriolis platform 17:08.680 --> 17:16.760 targeting fully automated design from second description sizing the parametric 17:16.760 --> 17:25.240 structure and eventually generating a working chip this is the project from united state they 17:26.040 --> 17:35.400 try to use machine learning AI to do automatic fully automatic layout generation this is the 17:35.400 --> 17:42.760 public project but unfortunately layer of machine learning models it's proprietary this was 17:42.760 --> 17:52.120 ran we together with Intel and as you can imagine Intel keeps all the models for themselves but we 17:52.120 --> 18:01.880 have framework to start with there is a lot of activities around it's a little bit chaotic so i'm 18:01.880 --> 18:09.080 glad that go IT project and fossil foundation free open source silicon foundation they 18:10.440 --> 18:17.080 define open source ideate route mark for europe this document has been submitted to brassel it's 18:17.080 --> 18:27.960 an evaluation and eventually would lead to new european level R&D project to cover this free domain 18:27.960 --> 18:38.040 open source analogs mix mode design productivity interoperability verification and third one digital 18:38.840 --> 18:46.680 system on chip this is at the digital level including open source tools so all what we are doing 18:46.680 --> 18:53.080 in open source tools i hope we'll be recognized and final support at european level 18:55.400 --> 19:03.080 all this teamwork this top list it probably does not include all who contributed to 19:03.080 --> 19:16.680 couple of points i was addressing R&D results is our team manager coordinating all in open 19:18.440 --> 19:26.760 open pdk in shot of a DHP serving under a lot of industrial experience and bringing this to 19:26.760 --> 19:35.480 open pdk domain we have partners at ith in story university technical university in linked 19:35.480 --> 19:42.040 i was referring to bomb by and they are also entering open pdk and we'll set up the tools 19:42.040 --> 19:51.720 to support our processes all it's open source it's not free so we are happy it's free to download 19:51.800 --> 19:59.000 and use but it's not free to develop so we we're happy that this was recognized in germany by local 20:01.480 --> 20:13.400 funding agency i i i'm glad that it was very first to support this activities and funding 20:13.480 --> 20:26.760 organization including micro electronics research funding organization and federal means of research 20:26.760 --> 20:37.000 and education in germany this contributors to open source route we have our partners from iHP 20:37.080 --> 20:44.680 contributing and their group of volunteers are edited jointly this proposal and again this is 20:44.680 --> 20:52.520 at evaluation in Brazil so if you want to learn more you are more than welcome to join us at 20:52.520 --> 21:02.920 serious of open pdk workshop session and different events around the world i hope to be 21:02.920 --> 21:07.960 transmitting you again and continue our discussion oh 21:13.640 --> 21:17.640 questions 21:24.520 --> 21:31.240 thank you for this beautiful presentation i have a question where can i find information for using 21:31.240 --> 21:46.840 iHP pdk with very low a i fan i from noting on the github so very low a models for semiconductor devices 21:48.520 --> 21:56.600 we are using psp MOSFET model in very low which is compile and it's part of 21:56.600 --> 22:05.160 angispice simulator and the same applies to edge bt models by polar transistor models which is 22:05.160 --> 22:18.360 vbic it was also compile it's part of angispice open pdk provides libraries and in libraries you 22:18.440 --> 22:27.640 have all parameters for these two transistors MOSFET and bipolar which you can design circuit and 22:27.640 --> 22:35.080 then eventually simulate with angispice we do not have very low a models for other components 22:36.920 --> 22:48.200 digital cells are represented as cell view with spice level net least for all digital blocks 22:48.440 --> 22:55.640 we do not have very low very low digital models for digital cells 23:02.520 --> 23:10.760 yes there should be should be link 23:18.760 --> 23:26.360 follow this link this is information about preparing here design for 23:29.160 --> 23:36.920 manufacturing with this for subsequent tape outs and if you follow there is 23:38.360 --> 23:45.960 installation information how to download open pdk from github how to install you build the 23:46.040 --> 23:54.120 three of libraries directory accessing the cells and they are a commendation how to configure it 23:54.120 --> 24:01.080 basic tools coax for schematic entry angispice or size for circuit level or transistor 24:01.080 --> 24:09.320 level simulation k layout all the tools validation verification tools for k layout so we have this 24:10.200 --> 24:16.440 flow it's not smooth transition from one step to another but it's already well established 24:17.320 --> 24:27.880 other tools for automatic design automatization of analog RFC I assist it's kind of work in 24:27.880 --> 24:36.280 products progress and we have this I wanted to free different platform which could automatize digital 24:36.360 --> 24:45.560 flow in case of digital design we are recommending open line and you start with your high level 24:45.560 --> 24:55.640 very lock CPU you can get risk five and then go through automatic synthesis and with 24:55.720 --> 25:05.960 generates your GDS 2 file targeted for iHP by CMOS process yes please 25:11.960 --> 25:16.600 okay I have lots more questions you mentioned that it's free to download but not free to 25:16.600 --> 25:23.160 manufacture so I don't know it's free to manufacture I also feel that this last QR code 25:23.880 --> 25:33.480 with offering free multi wafer multi project wafer runs so if you are student if you are 25:33.480 --> 25:41.640 academic partners you can submit your design will be verified validated if you qualify you will get 25:41.720 --> 25:55.640 free silica we cannot sell chip you are getting free loan of your chip there's simply 25:55.640 --> 26:03.480 legal procedure and in fact I HP owns your chip and you are getting this on the loan but 26:04.440 --> 26:12.120 then period is undefined so you you take your time to measure validate your chip now it's a 26:13.000 --> 26:24.280 it speeds federal R&D institution and cannot give something for free so we are offering the chips 26:24.280 --> 26:31.320 you design as loan for you to test you can share with your partners other who contribute to the 26:32.040 --> 26:37.000 but in the end if you want to go to the like full scale production is that also possible 26:37.000 --> 26:47.080 yes I HP have subsidiary which is called iHP solutions and they are coordinating low 26:47.080 --> 26:54.520 volume production and then of course we are coming to the business so it's other aspect more 26:54.600 --> 27:01.320 commercial aspect on the iC design and the links for all of this will be in your presentation 27:01.320 --> 27:06.760 yes I already have a blog so if you check out for them web page of our 27:07.800 --> 27:16.520 Deferum my slides are online each slides has corresponding link to all what I was present 27:16.840 --> 27:27.640 one last question maybe final one the rest in your PEDK you provide sales to the functions 27:27.640 --> 27:37.240 but if I design myself full custom sell and I want to integrate it in in a chip which is approved 27:37.240 --> 27:45.640 for your wafer run is that possible or yeah there are no risks that you can see this part like 27:47.400 --> 27:55.000 transistor or sell design flow independent so you will create your schematic representation 27:55.720 --> 28:04.920 spice net least and eventually layout which you have to verify do design roll check LBS parasitic 28:04.920 --> 28:13.640 extraction so you will be responsible for your new block or sell you are designing and then we 28:13.720 --> 28:21.880 have all tools to validate verify your new block but there is no risks yes there are any more questions 28:22.600 --> 28:30.280 yes I will be available and we will be happy to talk to you thank you very much very welcome thank you