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A number of weeks or months, depending on how much data you have in order to get a model.

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But really, this will not get you rich, this will give you a big electricity bill, a big

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hardware bill.

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But what will get you rich is the actual inference when people are querying that a

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base or doing some searches for something.

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So that's the point of the first line, trading is interesting, but inference is for

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her, and that's where you want to be effective in those accelerators.

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But of course, those accelerators go in big enterprise, data centers, and of course,

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you will waste lots of electricity on them, it can't stop.

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And of course, you need to have large engineering team.

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But, you know, it's totally possible to get into that business right now with risk five.

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Because when you look at this accelerator, it is a very simple design.

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You just take a basic processing element.

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You copy it a few times, a few dozen times, you know, and the thing is, if you have

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the proper IO's, then you have a chip perfectly, you know, capable to do that kind

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of inference at scale, you know, in a big enterprise data center.

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So maybe you start smiling, you grow, and, well, if you find the niche, other than boring

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ads, then maybe AI would be useful.

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So that's one way where, essentially, you could use risk five as this building block.

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Because of course, the AI specific sauce would be up to you, but anything which is

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generic computing that chip, you know, can be built using open source risk five designs.

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And that's the way to do it, because you don't want to reinvent the wheel with your own

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custom architecture for everything.

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Well, maybe this would be fun, but this would not be fast to market or profitable.

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Then, of course, the AI at the edge is a big topic.

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We have plenty of devices, all of you replace with built in AI, built in intelligence.

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And, well, a good example of that is this little AI chip by a sort of accelerer.

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So in that case, it's really a low power design, so you could run this in the field on

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battery powered, consumes just a few watts, okay, and probably if you would optimize it

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more, maybe it would go down up to a few million watts.

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And, well, that's great for a wide range of embedded, deeply embedded applications.

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In that case, the hardware is fairly small, so it could fit on a small M2 form factor

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board, okay, so a very small chip with the supporting components.

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And really, when you look at this, this is yet another very simple design.

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You have common building blocks with a risk of five controllers, and of course, security

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on the chip built in, because, well, if you are deploying this in the field, you need

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secure boot, you need accelerances that someone would rip off the device from the wall,

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let's say, wouldn't be able to access the data and be rich instead of you.

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Well, no, they are privacy implications and other like that, other things like that, of course.

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So really, the fact that the security is built in, in the case of this particular design

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is really fundamental, because you are deploying in the field, and so you need, you want

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to ensure that the data is private, and of course, that it stays really uncompromised.

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And, not your way to do this is to deal with, maybe, commercial vendors.

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So, for example, and desk technology, we'll known a risk-five vendor, they've got a number

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of risk-five cores, of course, but then they will happily license you their AI building

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blocks as well.

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So this is what industry to there, so you have a diagram for the type of core or chip

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that they would sell you.

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And of course, you know, they have an extensive software stack going well that, so they

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will provide you optimised compilers, real-time operating system, even an IDE if you want

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to use that, and what's wrong with them, anyway.

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All of that to say is you've got everything in the box to get you started more quickly,

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but in this case, their own business was only possible because risk-five was around providing

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this very stable foundation, and then they were able to build something that's really an

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interesting licensing place, so, you know, join the fund, that's yet another possibility

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for a startup if you are so inclined.

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And then, of course, there's plenty of AI in your pocket, right, and most phones today

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are able to do AI, but even for non-AI functions, have plenty of risk-five cores built

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in for power management, or screen management in the camera, all over the place, even

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fruity smartphones, so to speak, if you like, Apple's, you know, we'll have built-in

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risk-five controllers in the main SOC to do various things, right, and of course, they

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won't, they won't share that, those are not open source design.

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But all of that to say is that there are plenty of examples of, you know, using risk-five

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technology and build that into a more complex system to really deliver specialized things.

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So, if you build such a small AI accelerator, let's say that you want to embed into

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a non-based device, or even it's a device, you can do it, and once again, that's a business

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opportunity for you, and that's a business opportunity because, essentially, a risk-five

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is around and gives you a relatively free open building block to start with.

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But of course, well, that's a thing, risk-five is just the instruction set, and there

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are plenty of risk-five people that came on this stage earlier that will tell you about

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their marvelous boards and multiple scores and everything like that, but all of those

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things are proprietary, right, so you wouldn't necessarily have the source for that.

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So, what we do at Open Outwear Foundation is really to work on open source cores and even

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open source microcontrollers in one case, and provide those building blocks to the community,

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but at the same time, the focus is on industrial grades, so we do verification on those

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things, and I'm not the chip designer, Jeremy is, so we can tell you more about this aspect

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of things.

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Now, of course, you know, saying that we have risk-five cores could be anything, but really,

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in our case, the focus is really on smaller cores that go once again in a variety of embedded

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applications.

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Starting with CV2, which is roughly equivalent to the ARM Cortex M0, and then in the

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middle, the most popular family, let's say, so the CV4 family, where essentially we

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have equivalent for M4s or M2T3s on the arm side, and in this case, they are several variants

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with specific variations or specific feature sets, different from each other, but all of

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those are on GitHub in open source, and you can play with them and modify them, run them

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on FPGA, or even go get a chip made.

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And finally, CV6, CV6, in this case, runs Linux, so it's of course, a bigger and more powerful,

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and equivalent to ARM Cortex M0 or A55, in that case, so plenty of potential applications

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to all of those things, and of course, this is just what we have on the roadmap.

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We have, you know, longer-term plans for more powerful chips, eventually, in a can of

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stuff, so that's what you see, the CV8, for example, would be more powerful than all of

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those chips.

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So, once again, this, in the case of the open other Foundation, is a community driven

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set of projects, which means that, well, if you find this interesting and join, then

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we could go even smaller than the CV2, or even bigger than what CV8 is.

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This is all about, you know, bringing new members, bringing new ideas, and going where

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you want to go as a community.

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Once again, we are here, well, in my case, doing some part of the program management

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there to support our members in whatever they want to do.

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We don't necessarily dictate the technology direction.

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And so, what, will you find at Open Outwear Foundation, in terms of actual deliverables?

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Well, first, they are the course themselves.

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They are under the soldered pad license, which is roughly equivalent to the Apache tools,

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essentially.

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You take it, you do whatever you want with it, just put a small, a smaller, recognition

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in your readme somewhere that we've been around to provide you those building blocks.

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So the course are defined in system catalog, so you will find the false source code

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on GitHub.

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And then there's all the supporting infrastructure around it, right?

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So we have test benches, and of course, integration with most of the popular tools

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that are used by actual chip designers, and not, so please don't ask me about this.

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But once again, Dream is there, and it was more about those aspects than me.

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And of course, our friend Flow, so if you're wondering, it was on the talk, well, it's

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a really good thing for the first time.

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So, I'm here, instead.

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And so there's also a bunch of support software.

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So we work upstream with the TLVM and GCC and Jeremy will provide more details about that,

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but essentially we work upstream to ensure that our course are worth supported in those upstream

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tools.

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And then, of course, the open hardware foundation community worked on properly supported

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VRTOS support, for, of course, the smaller course.

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And we are starting to see an effort emerge around eclipse tradux as I will elaborate a bit

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later.

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And of course, there's plenty of documentation, and even board images for popular FPGA.

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So once again, if you want to modify the course, test them, then if you have one of those

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two FPGA's, well, the Nexus A7 will be appropriate for the CV-2 and 4, and the Genesis

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2, of course, for the CV-6, it's more expensive, but more powerful.

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You can actually boot Linux on that.

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Now of course, software will make and break your chip.

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And now it's Jeremy's time to shine, so I'll let us exchange a mic.

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Thank you, Frederick.

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Hopefully that's all good and clear.

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My background's more on the software side, so I'm going to talk about this.

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I'm co-chair of the technical work in group for open hardware foundation, which is

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the technical oversight for all the technical work we do.

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So within open hardware group, we break down into a small number of task groups to oversight

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to see the different areas we work on.

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We've got about five or six.

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The open hardware software task group is chaired by my colleague, Paolo Savini, and it's

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responsible for making sure that the software ecosystem we need is there around that chip.

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The tool chains, that's absolutely essential, but operating system ports where they needed

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any firmware that's needed for use the course and things like the SDK.

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And this continues to evolve and the work with ThreadX is just one of the latest things

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we're working on.

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It's a collaborative effort, it's open source, but it does rely on the member companies

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contributing to that effort.

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It's not just someone in their spare time, so that's been done both by companies like

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my and because I'm contributing, but also other companies actually funding us to contribute

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even more because they don't have a software team but they can buy us to do it as well.

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So that's how it's been done.

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In terms of the compilers, we've got GCC and Lofium, the goal is to go up stream.

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We don't want to maintain an out-of-tree compiler that is a whole world of pain of work

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closed.

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GCC 14.1 that came out last spring has five of the eight isher extensions for the CV-first

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costs of processor.

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There's three of them still in the review pipeline mostly because they're quite complex

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and the amount of review effort that's needed.

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KangelLVM18 has four of the extensions upstream that's running slightly behind.

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That work is largely done by our colleagues at the programming languages and compiler team

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of the Chinese Academy of Sciences.

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So that team has been a huge contribution there.

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They're all available to you, though,

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because we do maintain an out-of-tree mirror

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for the stuff that hasn't yet gone up soon.

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So if you go to the open hardware groups,

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GitHub, you will see that the source

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for the remaining out-of-tree materials,

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they're all the extensions are supported.

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And if you like your compile-a-tree change pre-made,

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you can download them from the Emboxon website.

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So how far have we got with the tool chains?

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Full assembler support, full built-in support,

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where it makes sense for some functions,

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it doesn't make sense to have built-in support.

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So that's due to efficiently.

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And for all but two of the extensions,

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we also have automatic code generation.

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We haven't yet got the code generation

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for the Bitmin population,

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because it is not standard Bitmin population.

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And we haven't yet got code generation

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for the SIMD instructions, but the rest of it's there.

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Operating systems are the QEMU port.

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That's a work in progress.

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Do come and join in if you'd like to help with that.

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There's free R-toss was done some time ago.

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There's work on going with Zepha.

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ThreadX, Frederick is much better qualified

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to talk about and he'll talk more about that later.

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There's no special Linux work,

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because actually we don't need anything special on Linux.

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It uses a standard Linux kernel,

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but for Dora and Red Hat have been working

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on then getting that all pulled together

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at a system level.

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So it all works on particularly CVACX.

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And last, you have an ID.

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Now this ID may not be, it is Ashley's risk free ID.

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So it's a well-established industry ID based on,

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in this case, eclipse, it'll actually run on other infrastructures,

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as well.

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But it's made available free for the open,

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for the open hardware foundation,

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and has the compilers, the debug, or everything built in.

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It does everything you'd expect,

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and you can just program in there.

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You can plug into your FPGA board and it just works.

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And well documented.

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We have an MCU.

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So in order to, we thought we'd make ourselves a reference MCU,

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so not just the processor,

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but some useful peripherals,

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so you've got some networking connections.

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You've got a timer, you've got buses to hook up to memory,

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and so forth.

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And that is the basis of the Core 5 Devkit,

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which is a Devboard.

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Now, I do have to say there's a slight catch here.

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The first version of the chip we spun

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had a metal layer error.

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We do have a small number of working chips,

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courtesy is a very clever laser use by our friends

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at the University of Saskatchewan,

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but there is a plan that this will be responding to you,

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course, and then we'll have a working silicon.

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So, and the idea of that is that we've got real

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a sick type hardware that goes faster

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and so forth, we can test things on.

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Now, I want to just end, because this is a talk

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about RIS 5 in AI, about an open source AI project,

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that is RIS 5, it's Core 5 based,

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and it is for the open.

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You can go and download this from GitHub.

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As a side interest, William Jones, who's my head of AI,

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and I, Supervisor Group Design Project,

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Southampton University, every autumn.

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So, we have six, four to six students working on a project.

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And we asked them a few years ago the question

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of everyone's building these AI accelerators based on RIS 5,

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which have the whole vector instruction set in,

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and they take vast acres of silicon.

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And that's not good for low-power applications,

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and really do you need the whole RIS 5 vector extension

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to accelerate AI.

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So, we said, how small can you make it?

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And they developed a derivative of CV-3040B,

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extended with just eight RIS 5 vector instructions,

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load and store, and one or two ads track multiplying and so forth.

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So, a tiny extension, and the result of that was,

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they got between a 5 and 7 fold speed up

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on the tiny ML-Perv benchmark.

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There is a video YouTube, they gave a talk

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to the British computer society about this work.

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It is the second most viewed video

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from the British computer society open source group.

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They're on YouTube, add all the sources on GitHub.

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And so, I put that there, not because it's particularly

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a software project, because I supervise it,

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and I was doing the software talk, so I think you came

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in the talk.

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So, with that, I'm going to hand back to Frederick.

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Thank you, all right.

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So, why would you come play with us, right?

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Because you want to get rich, you have ideas

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for our NEI startup, so why work in open source with us?

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Well, essentially, first, risk-5 is really changing

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the game in terms of what you can do with AI,

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because by using it as a building block,

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you can focus on your accelerator and on your added value

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on top, which means you get faster to market.

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And from that perspective, once again,

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it's one thing to have the I.C, but in our case,

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we provide you in this real great, verified course

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that you can leverage in your designs.

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And, of course, since the license is very permissive,

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you can use them as is, but you can improve on them, as well,

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right?

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And we hope that we get contributions back from that,

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but nothing in the license forces you to do so, okay?

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And really, the way that we operate is around three core values,

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open, transparent, and meritocratic.

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Open, being with everything in public, okay?

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There are no hidden mailing lists or hidden room,

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where you know the big guy stock, everything is done in the open, okay?

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Transparent, of course, means that we have public road maps,

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and I love that, you've seen the road map,

20:16.180 --> 20:18.660
and of course, there's more detail information

20:18.660 --> 20:20.940
on the open, other web foundation website.

20:20.940 --> 20:23.500
You can join the matter most in order to interact

20:23.500 --> 20:24.340
with the community.

20:24.340 --> 20:27.100
There are plenty of ways that you can find us.

20:27.100 --> 20:29.580
And even if you're not a member yet,

20:29.580 --> 20:31.380
you can interact with us.

20:31.380 --> 20:33.500
And meritocratic means that essentially,

20:33.500 --> 20:37.140
the people with commit rights on the repositories

20:37.140 --> 20:39.060
have to earn their way, right?

20:39.060 --> 20:40.940
They need to prove that they have the skills

20:40.940 --> 20:42.300
and that they've made contributions

20:42.300 --> 20:46.620
before becoming core committees on those projects.

20:46.620 --> 20:49.260
And a third big advantage of open-out web foundation

20:49.260 --> 20:52.220
is that it really brings together industrial players

20:52.220 --> 20:53.540
and academics.

20:53.540 --> 20:57.580
And to give you an example, I was traveling two weeks ago

20:57.580 --> 20:59.780
with Flow, we went to Montreal to put it

20:59.780 --> 21:01.180
at Technique Montreal.

21:01.180 --> 21:03.460
And we were visiting a professor there.

21:03.460 --> 21:06.900
He's got a project, a research project called Polara.

21:06.900 --> 21:11.700
And Polara was about making a physical chip out of the CVA6.

21:11.700 --> 21:16.700
So I've seen that very particular chip, okay?

21:16.700 --> 21:18.420
There's only an unfolding the word,

21:18.420 --> 21:22.340
and that was quite, quite impressive as a moment,

21:22.340 --> 21:25.260
because that was literally an open-source design

21:25.260 --> 21:28.860
on a chip that I could plug into,

21:28.860 --> 21:30.500
something and run the next on it.

21:30.500 --> 21:34.700
So of course, they are challenges, okay?

21:34.700 --> 21:38.980
And so to me, the technology needs to mature a little bit more,

21:38.980 --> 21:41.340
but this is an impressive achievement,

21:41.340 --> 21:43.980
and this is something that you could replicate yourself

21:43.980 --> 21:46.780
if you're thinking about starting a business.

21:46.780 --> 21:49.380
Of course, the cores are fully open.

21:49.380 --> 21:51.620
There's nothing hidden in there.

21:51.620 --> 21:54.540
And they are fully verified.

21:54.540 --> 21:58.140
So challenge our IRTL, if you want.

21:58.140 --> 22:01.460
But I mean, actual chip designers worked on this,

22:01.460 --> 22:03.620
and we have, of course, the verification,

22:03.620 --> 22:06.980
the validation reports to go with the technology.

22:06.980 --> 22:10.500
And finally, well, if you love Europe, I do.

22:10.500 --> 22:13.780
Then, well, open hardware foundation

22:13.780 --> 22:15.460
is a part of the Eclipse Foundation.

22:15.460 --> 22:17.940
The Eclipse Foundation is the largest open source

22:17.940 --> 22:19.340
organization in Europe.

22:19.340 --> 22:24.740
We have over 50% of our staff now in countries like France,

22:24.740 --> 22:27.820
and Germany, Sweden, Romania, Spain, Italy.

22:27.820 --> 22:29.860
So we're all available to place in Europe,

22:29.860 --> 22:31.700
and so we are close to you.

22:31.700 --> 22:33.620
We speak your language.

22:33.620 --> 22:36.900
It's a piston toy.

22:36.900 --> 22:38.860
I've known Poco is a Spaniard.

22:38.860 --> 22:41.420
Anyway, it's a part of our service.

22:41.420 --> 22:43.620
So I'll have that to say.

22:43.620 --> 22:45.660
The Eclipse Foundation, if you care about Europe,

22:45.660 --> 22:48.220
is the place to be.

22:48.220 --> 22:51.220
So my call to action, learned about core five,

22:51.220 --> 22:53.740
which is the name of our family, of course.

22:53.740 --> 22:55.900
And of course, the Open Outwear Foundation,

22:55.900 --> 22:56.820
visit the website.

22:56.820 --> 23:00.780
We've got a YouTube channel with lots of interesting videos

23:00.780 --> 23:03.740
that will get you acquainted with the technology, as well.

23:03.740 --> 23:04.860
Try the code on GitHub.

23:04.860 --> 23:09.460
The system very long is there, so if you're really a chip designer,

23:09.460 --> 23:12.500
please have a look and let us know what you think.

23:12.500 --> 23:13.500
And of course, engage.

23:13.500 --> 23:16.660
So that particular link, the slides are already in the tools.

23:16.660 --> 23:19.140
So when you click on it, you'll come to a section

23:19.140 --> 23:22.380
of our website where you have all the ways to interact with us.

23:22.380 --> 23:25.100
We'll find our references to the mailing lists,

23:25.100 --> 23:27.260
the matter most instances and everything

23:27.260 --> 23:30.260
that can get you connected into this.

23:30.260 --> 23:33.220
And now the last slide, what we're trying to achieve there

23:33.220 --> 23:37.260
by bringing Open Outwear Group into the Eclipse Foundation

23:37.260 --> 23:40.340
as the Outwear Foundation is to build this comprehensive

23:40.340 --> 23:43.420
and better risk-fifesteck, okay?

23:43.420 --> 23:46.740
From the course, to the tool chains like the compilers

23:46.740 --> 23:47.860
and we've seen with Jeremy,

23:47.860 --> 23:50.820
we're taking this upstream work really seriously.

23:50.820 --> 23:52.980
The real time operating systems

23:52.980 --> 23:56.020
and in particular, Eclipse 3DX, Eclipse 3DX

23:56.020 --> 24:00.540
is the only safety certified real time operating system,

24:00.540 --> 24:02.740
which is also open source in the market.

24:02.740 --> 24:04.340
So you can put it in cars.

24:04.340 --> 24:06.660
You can put it in home appliances.

24:06.660 --> 24:09.340
You can put it in medical devices today,

24:09.340 --> 24:12.900
not two, three, four years away.

24:12.900 --> 24:15.220
Like it would be the case with the affair,

24:15.220 --> 24:18.940
but literally today we've got the certificates to prove it, okay?

24:18.940 --> 24:21.500
So in this case, we are starting this effort

24:21.500 --> 24:26.500
to port it to Core 5 and specifically the CV4 family

24:27.860 --> 24:30.140
and eventually CV6 maybe.

24:30.140 --> 24:33.100
Anyway, and also of course,

24:33.100 --> 24:34.700
the Eclipse Foundation traditionally

24:34.700 --> 24:36.380
was all about development tools.

24:36.380 --> 24:39.020
So the traditional Eclipse IDE is still around,

24:39.020 --> 24:42.140
but we've got also Eclipse TA, Eclipse TA

24:42.140 --> 24:46.460
is like visuals to do called minus the Microsoft

24:46.460 --> 24:49.180
and it's integrated with Open VSX,

24:49.180 --> 24:52.860
which is a vendor neutral extension repository,

24:52.860 --> 24:56.260
not controlled by anyone but owned by the Eclipse Foundation

24:56.260 --> 24:58.340
on behalf of the Open source community.

24:58.340 --> 25:01.820
So if you truly believe in a hardcore open source

25:01.820 --> 25:03.860
approach and so to speak,

25:03.860 --> 25:06.140
you've got all of the pieces there in the open.

25:06.140 --> 25:10.220
And so this is not about just the traditional Eclipse IDE,

25:10.220 --> 25:14.540
but really forward-looking technologies.

25:14.540 --> 25:16.980
And of course, there's the rest of the Eclipse family.

25:16.980 --> 25:20.420
So I'm also responsible for the Eclipse IoT working group.

25:20.420 --> 25:23.140
So if you want an MQTT broker or something like that,

25:23.140 --> 25:25.940
then you can go there on the problem.

25:25.940 --> 25:28.460
And of course, we've got a full-blown software

25:28.460 --> 25:29.860
to find vehicle working group.

25:29.860 --> 25:33.180
So if you're thinking about doing AI

25:33.180 --> 25:36.420
but around the automotive, then of course,

25:36.420 --> 25:39.140
our SDB working group is a place to be.

25:39.140 --> 25:41.140
So thank you very much.

25:41.140 --> 25:43.100
It's been a pleasure to be with you today.

25:43.100 --> 25:45.540
And now we've got some time for questions.

25:45.540 --> 25:46.700
So.

25:46.700 --> 26:05.020
So it seems the question microphone is dead.

26:05.020 --> 26:06.780
OK, we'll repeat the questions then.

26:06.780 --> 26:09.580
So please ask, I will repeat for the people online.

26:09.580 --> 26:30.380
So the question here is the CV-2 and 4 families.

26:30.380 --> 26:34.020
They are for embedded in CV-6 for more powerful things.

26:34.020 --> 26:35.180
And yes, that's OK.

26:35.180 --> 26:37.220
So CV-6 runs Linux.

26:40.540 --> 26:58.540
So the question is why is the CV-4 or even CV-2 supporting

26:58.540 --> 27:01.500
on the 32 bits?

27:01.500 --> 27:02.420
That's a good question.

27:06.020 --> 27:06.780
It's enough.

27:06.780 --> 27:08.860
I think for the applications.

27:08.860 --> 27:13.100
If a member came along and said I wanted to build a 64-bit embedded

27:13.100 --> 27:15.820
class processor, sure, that would be fine.

27:15.820 --> 27:19.260
The intention is the CV-6, which comes in 30 to 60

27:19.260 --> 27:24.300
before the versions, is intended for application classes.

27:24.300 --> 27:27.900
Of course, a typical microcontroller would be a few hundred

27:27.900 --> 27:33.740
megahertz in clock frequency and maybe one megabyte of memory

27:33.740 --> 27:37.020
or maybe five hundred, five hundred and twelve keys.

27:37.020 --> 27:41.900
So in that case, even if the processor

27:41.900 --> 27:45.180
core itself would be 64 bits, then it would be overkill.

27:45.180 --> 27:49.260
And maybe it's a bit more power efficient to stay on 32 bits

27:49.260 --> 27:52.700
for that kind of embedded application as well.

27:52.700 --> 27:53.900
Yes?

27:53.900 --> 27:55.180
Yes.

27:55.180 --> 27:58.460
Is there a way to turn a better one in the next open neural network

27:58.460 --> 28:04.140
or change format to the core specific instructions?

28:04.140 --> 28:08.060
So the question here is, is it possible to convert

28:08.060 --> 28:11.660
from the open network in X?

28:11.660 --> 28:12.460
Oh, sorry.

28:12.460 --> 28:13.500
Oh, yeah.

28:13.500 --> 28:16.620
So the question is about ONNX, which is the open neural network

28:16.620 --> 28:17.900
exchange format.

28:17.900 --> 28:22.700
The, that has not been investment yet in the tool chain

28:22.700 --> 28:23.660
to develop for that.

28:23.660 --> 28:25.260
I recommend to the talk.

28:25.260 --> 28:28.140
I'm going to be with William Jones tomorrow afternoon in the AI

28:28.140 --> 28:30.300
on how to do that, which is an example.

28:30.300 --> 28:32.780
Again, I think example project from Southampton University

28:32.780 --> 28:34.940
is it happens on how we'll do that.

28:34.940 --> 28:37.900
But yeah, that's generally a problem for anything

28:37.900 --> 28:38.940
that's not an Nvidia chip.

28:57.260 --> 29:00.420
So your question or comment is about the fact

29:00.420 --> 29:06.740
that in terms of PCI express support, they are not,

29:06.740 --> 29:11.460
let's say they are no good open source alternatives

29:11.460 --> 29:13.060
currently that you could leverage.

29:13.060 --> 29:14.060
Is that it?

29:14.060 --> 29:17.060
The problem is not from this task, because me and my team

29:17.060 --> 29:22.660
we kind of take on $1,000 of the complex IP

29:22.660 --> 29:26.660
for PCI experts, so all can be too today.

29:26.660 --> 29:31.300
OK, so it's very expensive to get access to the IP

29:31.300 --> 29:34.260
for, you know, let's say a PCI express controller.

29:34.260 --> 29:37.940
And so you're asking what you could do about that

29:37.940 --> 29:39.780
in terms of implementing something.

29:39.780 --> 29:43.620
Not sure if some members worked on such things.

29:43.620 --> 29:45.860
I was saying more on the software side.

29:45.860 --> 29:47.940
I mean, it's a general problem with peripheral hardware.

29:47.940 --> 29:51.220
It's been forever going back to open calls days

29:51.220 --> 29:56.100
that actually well-beating high performance peripherals

29:56.100 --> 29:58.580
are really hard to design, and that hasn't

29:58.580 --> 30:01.540
been a big enough community to do open source versions.

30:01.540 --> 30:03.700
I'm sure if anyone would like to contribute a state

30:03.700 --> 30:08.020
of the art high performance PCI, any sort of PCI express

30:08.020 --> 30:09.940
interface we'd love to have it, and we'd

30:09.940 --> 30:13.780
I'm sure welcome it as a part of the open hardware foundation.

30:13.780 --> 30:15.460
But I don't know of an implementation.

30:15.460 --> 30:16.740
Does anyone in the room know if an open

30:16.740 --> 30:19.460
high performance implementation is open source?

30:19.860 --> 30:28.580
Yeah, so the session like such, it has something that might help

30:28.580 --> 30:29.860
towards that, that's good.

30:29.860 --> 30:37.460
But it is PCI 2X, not PCI 3X, so PCI 2X, not PCI 3X, okay?

30:37.460 --> 30:39.460
Okay?

30:39.460 --> 30:42.260
Yeah, I have a question.

30:42.260 --> 30:44.500
Oh, okay.

30:44.500 --> 30:48.820
So are there any plans of aping out CES6?

30:48.820 --> 30:55.620
You already taped out, I understand the 32 bit MCU, somehow the

30:55.620 --> 31:00.580
like you explained the PCI 3X, the boat is not available,

31:00.580 --> 31:02.980
maybe only available to members internally.

31:02.980 --> 31:07.140
But taping out CES6 hasn't been pride, or is it still

31:07.140 --> 31:10.580
let's say on the ideal side, and let's say never on an ASIC,

31:10.580 --> 31:13.060
or GDS, it hasn't seen a found rate.

31:13.060 --> 31:16.020
What is the plan going there?

31:16.020 --> 31:20.580
So just in case the microphone wasn't loud enough for people online.

31:20.580 --> 31:24.820
So the question is essentially if we are planning to tap out

31:24.820 --> 31:31.540
have a physical chip of the CVA6, because in the case of the CVA4,

31:31.540 --> 31:36.740
something something, in the context of the core 5 MCU we had,

31:36.740 --> 31:39.540
those physical chips, I have a non-working board,

31:39.540 --> 31:43.380
unfortunately with me in my back, I wish it would work.

31:43.380 --> 31:52.580
But in the case of the core 5 MCU and the dev kit board that we've shown,

31:52.580 --> 31:57.940
in fact, I think the PCB design for this is open as well, right?

31:57.940 --> 32:03.220
Yeah, so everything, everything that we could make publicly available is.

32:03.220 --> 32:07.300
But do we have the same type of plan for the CVA6 to my knowledge, no?

32:07.300 --> 32:11.940
But I think the CVA4, I mean, that small,

32:11.940 --> 32:15.460
it was easy, and it was done with the support of quick logic and silicon labs

32:15.460 --> 32:19.540
to get it out the door, it's expensive to do that.

32:19.540 --> 32:24.900
The CVA6, however, is being heavily used in a number of European research projects,

32:24.900 --> 32:29.780
and I anticipate that those projects, so we've got any of the CVA6 people here,

32:29.780 --> 32:32.420
there we haven't got them in the room, but I believe as some of those,

32:32.420 --> 32:34.820
they will be doing some degree of taping out.

32:34.820 --> 32:38.900
But I think you have to go and look at those specific projects last.

32:38.900 --> 32:43.060
Of course, I mean, we could be creative eventually about that,

32:43.060 --> 32:46.820
you know, and I'm just rambling off without the actual bus, you know,

32:46.820 --> 32:52.020
flow being, you know, in Taiwan and all, you know,

32:52.020 --> 32:56.980
if there's community demand from a number of, you know, companies that we're willing to

32:56.980 --> 33:01.620
pull resources in order to make that happen, we would, of course, consider it, right?

33:01.860 --> 33:05.060
But as Jeremy said, this is an expensive endeavor,

33:05.060 --> 33:09.220
so if you want physical chips, you better join, and tell your friends to join,

33:09.220 --> 33:12.740
etc. and then we get the money to make that happen,

33:12.740 --> 33:16.740
because that's one of the things that I noticed in today's many presentations.

33:16.740 --> 33:18.340
I'm coming to your question.

33:19.620 --> 33:23.780
There's a lack of good, you know, validated boards or easily

33:23.780 --> 33:28.900
of the obtainable boards in the market right now for people willing to work with this technology.

33:28.900 --> 33:32.180
So maybe we can fix that as an open community.

33:32.180 --> 33:32.980
So sir.

33:38.980 --> 33:41.220
Well, we are members of the RISFF Foundation.

33:41.220 --> 33:43.700
We are on a number of their committees.

33:44.660 --> 33:46.180
Maybe Jeremy knows which one.

33:48.180 --> 33:50.580
Individual members, most members of Open Hub,

33:50.580 --> 33:53.300
with my company, for example, I'm members of RISFF International,

33:53.300 --> 33:56.260
and will be on committees there.

33:56.340 --> 33:58.420
And there is engagement with chief executive,

33:58.420 --> 34:00.260
level to chief executive, of the CTA,

34:00.260 --> 34:01.380
trying to coordinate what we do.

34:01.380 --> 34:03.860
And indeed with the RISF Foundation and other organizations,

34:03.860 --> 34:05.460
it's not just RISF.

34:07.460 --> 34:11.220
So we're one big appeal, open family, so to speak.

34:12.500 --> 34:12.900
Yes.

34:22.900 --> 34:25.060
That, I have no idea.

34:26.020 --> 34:28.660
So the question is which PDK flow and I don't have an idea.

34:28.660 --> 34:31.220
At this point, it comes clear, I'm not really a hard-wrenching there.

34:31.220 --> 34:34.900
So the answer is I don't know, but it's a question we can take away and get the answer back.

34:44.580 --> 34:46.900
There is people who have looked at that and the open hardware,

34:46.900 --> 34:49.940
the print open source silicon foundation has regularly had key

34:49.940 --> 34:52.580
stock projects to try and actually get this fully open.

34:52.660 --> 34:56.580
The actual defined flows, though, are not open source.

34:56.580 --> 35:00.580
They use synopsis UVM flow, I think.

35:00.580 --> 35:04.420
So I'd love it, I'd love it if someone wants to pick that up,

35:04.420 --> 35:05.620
and you can do it.

