WEBVTT 00:00.000 --> 00:11.000 All right, Felix, you ready? 00:11.000 --> 00:13.000 All right. 00:13.000 --> 00:14.000 Good morning. 00:14.000 --> 00:17.000 Our first talk of the day is from Felix. 00:17.000 --> 00:21.000 Felix is a researcher and free software supporter currently working on the Vera 00:21.000 --> 00:25.000 Log AMS in GNUCAP with funding from NL nets. 00:25.000 --> 00:27.000 Thanks, Felix. 00:28.000 --> 00:29.000 Thank you. 00:29.000 --> 00:31.000 Thanks, Chris, for the introduction. 00:31.000 --> 00:33.000 Thanks for organizing this event. 00:33.000 --> 00:37.000 Thanks, everyone, for coming at this early hour. 00:37.000 --> 00:41.000 I would like to talk about GNUCAP again, 00:41.000 --> 00:44.000 and what happened since last first and basically, 00:44.000 --> 00:46.000 giving a quick summary. 00:46.000 --> 00:49.000 And thanks to NL nets, 00:49.000 --> 00:52.000 most, because this wouldn't happen without NL nets. 00:52.000 --> 00:55.000 There was lots of tinkering before 00:55.000 --> 00:58.000 and it came entering the scene. 00:58.000 --> 01:03.000 And I think that's an important aspect of this whole thing. 01:03.000 --> 01:07.000 So an extra thanks goes to Amsterdam. 01:07.000 --> 01:10.000 And so what is this about? 01:10.000 --> 01:14.000 The GNU circuit analysis package is a small package. 01:14.000 --> 01:16.000 We do circuit analysis. 01:16.000 --> 01:20.000 We extend the library with plugins, 01:20.000 --> 01:22.000 which I will explain in a bit. 01:23.000 --> 01:27.000 And it was originally meant as a different spice, 01:27.000 --> 01:29.000 like simulator to simulate stuff, 01:29.000 --> 01:32.000 but on smaller machines, smaller hardware demands, 01:32.000 --> 01:33.000 and stuff. 01:33.000 --> 01:35.000 And it brought a model compiler, 01:35.000 --> 01:38.000 which allowed you to describe models 01:38.000 --> 01:41.000 and run them with your simulation. 01:41.000 --> 01:44.000 And the bit of the extra here is, 01:44.000 --> 01:46.000 we do post-spice simulation. 01:46.000 --> 01:49.000 We use new algorithms, new concepts, 01:49.000 --> 01:52.000 and towards mixed simulations, 01:52.000 --> 01:56.000 and doing things faster than other simulators do. 01:56.000 --> 01:59.000 And it started in 1990 with ACS. 01:59.000 --> 02:01.000 That's else circuit simulator Alice. 02:01.000 --> 02:04.000 As here, he couldn't join us last year, 02:04.000 --> 02:06.000 but if you have questions to him, 02:06.000 --> 02:09.000 you can ask him maybe not after the session. 02:09.000 --> 02:13.000 He released his software in 2001 under GPL license 02:13.000 --> 02:15.000 to avoid patent issues. 02:15.000 --> 02:20.000 And that's maybe part of the deal. 02:20.000 --> 02:23.000 We have stuff that others don't, 02:23.000 --> 02:25.000 and others would like to have, 02:25.000 --> 02:26.000 but don't. 02:26.000 --> 02:30.000 And L decided to move to plugins 10 years after 02:30.000 --> 02:33.000 in order to make it more kind of community friendly. 02:33.000 --> 02:35.000 Without funding, that wasn't possible, 02:35.000 --> 02:38.000 and funding started three years ago. 02:38.000 --> 02:40.000 And so why circuits? 02:40.000 --> 02:42.000 We simulate circuits, 02:42.000 --> 02:46.000 it's part of the design process of chips, 02:46.000 --> 02:49.000 and everything that depends on chips, PCBs, 02:49.000 --> 02:51.000 or circuits in general. 02:51.000 --> 02:53.000 And we want more of them, 02:53.000 --> 02:57.000 and commercial tools do this all the time, 02:57.000 --> 03:01.000 and free software is a bit lagging behind. 03:01.000 --> 03:06.000 And part of the problem is missing standardization. 03:06.000 --> 03:08.000 There's been some standardization work 03:08.000 --> 03:11.000 in programming languages in the past decades, 03:11.000 --> 03:15.000 which kind of missed out on circuit simulation 03:15.000 --> 03:17.000 and hardware description. 03:17.000 --> 03:21.000 And everyone, it invents their own hardware description language. 03:21.000 --> 03:27.000 And some companies set together and decided to write up a standard 03:27.000 --> 03:31.000 to simulate, or to verify first, 03:31.000 --> 03:36.000 the circuit relevant models 03:36.000 --> 03:39.000 and came up with very log 95, 03:39.000 --> 03:44.000 and everyone probably knows from small logic simulations. 03:44.000 --> 03:47.000 And later variants have come up, 03:47.000 --> 03:52.000 and people have kind of collectively created models 03:52.000 --> 03:55.000 or could exchange data and simulate them, 03:55.000 --> 03:58.000 and do similar things with similar results. 03:58.000 --> 04:02.000 And a very log AMS is the analog mixed signal extension 04:02.000 --> 04:04.000 for very log 95, 04:04.000 --> 04:08.000 which adds what spies had to the very log 95, 04:09.000 --> 04:12.000 and adds some interconnect layers, 04:12.000 --> 04:18.000 and modeling for stuff in between the analog and digital domain. 04:18.000 --> 04:20.000 And we just do it that way, 04:20.000 --> 04:23.000 because we have no time to reinvent the wheel. 04:23.000 --> 04:27.000 Plugins, everyone knows plugins from Linux, from Python. 04:27.000 --> 04:29.000 We do it basically the same way. 04:29.000 --> 04:32.000 We have an interface that loads plugins. 04:32.000 --> 04:34.000 We allow everyone to build their own plugins. 04:34.000 --> 04:37.000 We don't care what they do really. 04:38.000 --> 04:41.000 And if you have plugins, you can share them with others 04:41.000 --> 04:43.000 and let others run your stuff. 04:43.000 --> 04:46.000 You don't need to bother with upstream development, 04:46.000 --> 04:49.000 or you don't need to bother with completing them. 04:49.000 --> 04:51.000 You have a proof of concept. 04:51.000 --> 04:52.000 You can talk about it. 04:52.000 --> 04:54.000 You can present it. 04:54.000 --> 04:58.000 And we have some existing examples, 04:58.000 --> 05:01.000 some of which are built into the main repository. 05:01.000 --> 05:05.000 And we have some satellite repositories or branches with other stuff. 05:05.000 --> 05:10.000 And the new stuff that has happened since last, 05:10.000 --> 05:15.000 for us them is we have now we have no ordering plugins, 05:15.000 --> 05:18.000 because no ordering is a hard problem. 05:18.000 --> 05:21.000 Everyone who can do better will come and do better. 05:21.000 --> 05:22.000 Show us your plugin. 05:22.000 --> 05:27.000 We have a KLU plugin, KLU is one of these general purpose matrix solvers, 05:27.000 --> 05:33.000 which turned out to be nice for small analog circuits. 05:33.000 --> 05:36.000 And we are waiting a new version of KLU. 05:36.000 --> 05:39.000 We already have the interface for it. 05:39.000 --> 05:42.000 And whatever you want to do. 05:42.000 --> 05:46.000 So we have these goals here at the standardization, 05:46.000 --> 05:48.000 the very log model gen. 05:48.000 --> 05:55.000 The support for very log AMS splits into the simulator support 05:55.000 --> 05:57.000 and the model compiler support. 05:57.000 --> 06:02.000 And we want to kind of make other people standardize their workflows 06:02.000 --> 06:06.000 to make tools more transparent and stuff. 06:06.000 --> 06:10.000 And that's why the first topic today is five formats again. 06:10.000 --> 06:17.000 And the second and third topic is about advancements in the simulator 06:17.000 --> 06:19.000 and model compiler. 06:19.000 --> 06:23.000 And I've got some working progress on stuff, 06:23.000 --> 06:28.000 particularly other people jumping on board and doing great stuff. 06:28.000 --> 06:30.000 And I want to get into that a bit. 06:30.000 --> 06:35.000 So why do we need a file format for data interchange? 06:35.000 --> 06:38.000 It has been puzzling many for many years, 06:38.000 --> 06:41.000 but to build a chip or anything more complex, 06:41.000 --> 06:45.000 you need multiple tools and you want to get your data across. 06:45.000 --> 06:48.000 And when you watch circuit designers, 06:48.000 --> 06:51.000 there's one group that uses commercial tools. 06:51.000 --> 06:56.000 The commercial tools are driven by armies of developers who write converters 06:56.000 --> 06:59.000 and nobody in the open source or free software world 06:59.000 --> 07:03.000 can be really bothered with, 07:03.000 --> 07:06.000 I don't know, with catching up really. 07:06.000 --> 07:09.000 So everyone catches up but in different directions. 07:09.000 --> 07:13.000 So there's no common denominator and it's a bit of a mess. 07:13.000 --> 07:21.000 And people are validating data exports more than they do real work. 07:21.000 --> 07:25.000 And the other problem is the one way conversions. 07:25.000 --> 07:29.000 You do a conversion one way, you send some schematic to some simulator 07:29.000 --> 07:32.000 and you never get it back into the schematic. 07:32.000 --> 07:37.000 And then you start inventing workarounds for that. 07:37.000 --> 07:42.000 And that's just the example I want to get into in more detail now. 07:42.000 --> 07:45.000 And a schematic is nothing but the circuit, 07:45.000 --> 07:48.000 but it does have coordinates attached to it. 07:48.000 --> 07:52.000 So why not just use circuits instead of drawings. 07:52.000 --> 07:56.000 And drawings is something that you can forget. 07:56.000 --> 08:00.000 If you miss out on a drawing, it's still the circuit that you want to design. 08:00.000 --> 08:07.000 And the syntax we chose for this proposed format is based on very log 08:07.000 --> 08:12.000 because it has a history in this area, very log 95. 08:12.000 --> 08:17.000 I mean, that's a year, that's like 30 years ago and more. 08:17.000 --> 08:23.000 And if you do it that way, you could use the same circuit and just go with it. 08:23.000 --> 08:32.000 And a very log S is the kind of standard extension name that we dub it very log S 08:32.000 --> 08:36.000 because it's very log and it has some extras. 08:36.000 --> 08:43.000 The S is schematic and there has been early work as early as 2012. 08:43.000 --> 08:49.000 There was a summer of code student who started to try and import Gida plugins 08:49.000 --> 08:55.000 which prompted L to think about it more and he gave a talk here 10 years ago. 08:55.000 --> 09:06.000 And we put it on our proposal in 23 to extend on that work and build up this standard document, 09:06.000 --> 09:09.000 which is now a means partly complete, 09:09.000 --> 09:14.000 but it works the way you would need it for what we want to do. 09:14.000 --> 09:19.000 And we have support in the simulator and model compiler for so-called same party vices, 09:19.000 --> 09:22.000 which I will go and explain in a bit. 09:22.000 --> 09:32.000 And it's also very log S support in a satellite project that David did from what was that. 09:32.000 --> 09:39.000 He's also NGI funded and he wanted to use Quacks for schematic editing stuff 09:39.000 --> 09:43.000 and used Nukep and we kind of collaborated on some patches to Quacks. 09:43.000 --> 09:49.000 And then there's very log S support there now which is usable but not complete. 09:49.000 --> 09:58.000 And I hacked on this Nukep Gida project which came out of this group of summer of code project in 2012 09:58.000 --> 10:05.000 and we do have non-circuit item support so you can have proper schematics with everything attached to them 10:05.000 --> 10:09.000 and go back and forth between different presentations. 10:09.000 --> 10:13.000 And what else is there that needs doing. 10:13.000 --> 10:25.000 Lapton is what was GDA, GDA and or Gida and we were talking about adding very log S support to that too 10:25.000 --> 10:29.000 and they're political problems with that. 10:29.000 --> 10:34.000 It would be nice if somebody took over Quacks and finished that work 10:34.000 --> 10:39.000 and other schematic editor programs should also move forward. 10:39.000 --> 10:43.000 So the same party vices that we have added support to. 10:43.000 --> 10:47.000 Yeah, what are nets? In spice nets don't exist. 10:47.000 --> 10:54.000 In schematics nets are like drawings and lines and in very log 95 or surprise, 10:54.000 --> 11:00.000 they have been standardized and they have a proper meaning and they are supported. 11:00.000 --> 11:06.000 And implemented since forever in tools that do discrete digital stuff. 11:06.000 --> 11:13.000 And it hasn't been propagated to the analog folks unfortunately, 11:13.000 --> 11:20.000 which means we can't really, we can't do much with schematics without nets. 11:21.000 --> 11:26.000 In Quacks there are kind of traces in the code that indicate that it might have been intended. 11:26.000 --> 11:30.000 We have hacked that and it's not working. 11:30.000 --> 11:37.000 And very log has this nice description for a same port device which just means we have name ports 11:37.000 --> 11:40.000 and we have internal nodes in the module. 11:40.000 --> 11:44.000 And we can connect them anyway we want which also gives it which already gives us a net. 11:44.000 --> 11:47.000 And every schematic has these everywhere. 11:47.000 --> 11:52.000 And now we can represent them so our schematic becomes circuit. 11:52.000 --> 11:54.000 I mean the drawing. 11:54.000 --> 11:58.000 So the simulator has worked weight. 11:58.000 --> 12:02.000 This was the file format and data exchange. 12:02.000 --> 12:05.000 So this is the next topic and advancements in the simulator. 12:05.000 --> 12:10.000 Most of it was algorithmic and low level stuff that we have added. 12:10.000 --> 12:13.000 And some is actually visible to users. 12:13.000 --> 12:17.000 We have this circuit topology stuff supported in full. 12:17.000 --> 12:21.000 So you can now read in the schematics last year at first them. 12:21.000 --> 12:25.000 I said oh there's this work around and we can simulate quacks stuff and stuff. 12:25.000 --> 12:31.000 And now we can actually read in the files that quacks saves and simulate them. 12:31.000 --> 12:35.000 We have integration methods selection which I will explain. 12:35.000 --> 12:40.000 We have data shared across identical devices which is important for scaling. 12:40.000 --> 12:45.000 Some minor stuff that yeah the node orderings are plug-able. 12:45.000 --> 12:49.000 That was a kind of a bigger lift but it's not as user visible. 12:49.000 --> 12:52.000 It's something that researchers might be interested in. 12:52.000 --> 12:56.000 And the matrix interface and stuff. 12:56.000 --> 13:01.000 And you can now pass big spicy net lists which kind of choke the system. 13:01.000 --> 13:04.000 Because why would we want to do that anyway. 13:04.000 --> 13:06.000 But now it's possible. 13:06.000 --> 13:10.000 There are still working towards the advent driven stuff. 13:10.000 --> 13:15.000 And all the other very log AMS features related to that. 13:15.000 --> 13:17.000 The messages it will come. 13:17.000 --> 13:18.000 It's on my list. 13:18.000 --> 13:19.000 It's on my desk. 13:19.000 --> 13:21.000 It's more than half finished. 13:21.000 --> 13:23.000 It's much more finished than last year. 13:23.000 --> 13:27.000 And yeah we are on track. 13:27.000 --> 13:33.000 It's not easy because if it was easy it would be called football. 13:33.000 --> 13:34.000 I don't know. 13:34.000 --> 13:38.000 So let's go to the algorithms here. 13:38.000 --> 13:40.000 The nets. 13:40.000 --> 13:44.000 In practice these nets have different models. 13:44.000 --> 13:50.000 So we want them to be first class devices in a model for different reasons. 13:50.000 --> 13:55.000 One is we want them to be a drawing and mischematic. 13:55.000 --> 14:00.000 It doesn't really, we don't really know what users will do with them. 14:00.000 --> 14:07.000 The application is going to decide and whether a net is a transmission line or a short 14:07.000 --> 14:10.000 really depends on what analysis you're going to do. 14:10.000 --> 14:15.000 So we need them explicit regardless and we have this module net. 14:15.000 --> 14:19.000 We can use, we can do the schematic drawings. 14:19.000 --> 14:26.000 And this union find algorithm is now in place in the in the library. 14:26.000 --> 14:33.000 And it curves out the actual technology of the circuit that is needed. 14:33.000 --> 14:39.000 And we have added these spice style things. 14:39.000 --> 14:44.000 I mean we do have this spice subsystem in GNUKAP because the very log stand at one step. 14:44.000 --> 14:46.000 It's not because spice is fun. 14:46.000 --> 14:49.000 But we want to support spice. 14:49.000 --> 14:55.000 And if you have a spice net list, we basically want to run it or understand it. 14:55.000 --> 14:59.000 It's unmodified. 14:59.000 --> 15:06.000 So you don't need to change your data. 15:06.000 --> 15:10.000 You can just keep using it the way it is. 15:10.000 --> 15:18.000 The integration method selection is a deeper problem from signal processing. 15:18.000 --> 15:23.000 In analog simulation, you have this problem with time steps and integration method. 15:23.000 --> 15:28.000 Integration methods, if you have like capacitors or coils in your circuit, 15:28.000 --> 15:33.000 and something has inertia and stuff you need to integrate stuff. 15:33.000 --> 15:37.000 And there are different methods that represent the rule. 15:37.000 --> 15:42.000 I mean it's like if you integrate and you measure the area under your curve, 15:42.000 --> 15:46.000 you can use this trapezoidal method. 15:46.000 --> 15:50.000 And it's very nice if your signals are clean and smooth. 15:50.000 --> 15:53.000 And fast allows for big time steps. 15:53.000 --> 15:56.000 And if there is a king, it is continuity. 15:56.000 --> 16:01.000 Some discrete signal saying, oh no, this signal is suddenly something else. 16:01.000 --> 16:05.000 It starts ringing because of high frequency components and stuff. 16:05.000 --> 16:11.000 And people from the spice world have come up with some other methods that damps out discontinuities. 16:11.000 --> 16:12.000 They call it gear. 16:12.000 --> 16:15.000 And they switch to gear whenever it rings. 16:15.000 --> 16:16.000 And they do it globally. 16:16.000 --> 16:19.000 So the whole circuit now runs with gear. 16:19.000 --> 16:21.000 And then dissipates energy. 16:21.000 --> 16:24.000 So the results are suddenly questionable. 16:24.000 --> 16:26.000 So we need to make choices here. 16:26.000 --> 16:34.000 And in GNUKAP, this choice was made like 30 years ago that we need this option per device on the user level. 16:34.000 --> 16:41.000 And not for someone who can write a C model for each case or for each stuff it does. 16:41.000 --> 16:50.000 So we can now select the integration method at a fine granularity at the user level. 16:50.000 --> 16:56.000 And for this, we need the very log input language because the very log input language has support for system parameters. 16:56.000 --> 16:58.000 And system parameters can have extensions. 16:58.000 --> 17:01.000 So we can add an extension that does that. 17:01.000 --> 17:06.000 And for large simulations, this would be necessary. 17:06.000 --> 17:13.000 And so we are moving ahead with stuff we need for large mix simulations. 17:13.000 --> 17:20.000 And that concludes my simulator stuff that is new. 17:20.000 --> 17:26.000 And I'm going to explain a bit more about the model compiler. 17:26.000 --> 17:31.000 Model compiler kind of extends the whole system by the behaviors. 17:31.000 --> 17:34.000 The subset support for very log AMS. 17:34.000 --> 17:49.000 Behavioral modeling support is the bit in very log AMS that allows you to describe your devices using differential equations and assignments and delays and operators and stuff. 17:49.000 --> 17:54.000 And in order to run them, you need to turn them into byte code. 17:54.000 --> 17:56.000 We turn them into C++ code. 17:56.000 --> 18:00.000 We compile them with GCC and we load them into Gnucab as plugins. 18:00.000 --> 18:07.000 And model gen very log is the part that turns behavioral descriptions into C++ code. 18:07.000 --> 18:09.000 And that can be loaded. 18:09.000 --> 18:16.000 And the work we are doing here is based on the model gen, which is the original model compiler, 18:16.000 --> 18:23.000 which coincidentally has influenced the way very log AMS looks now, but nobody has finished it. 18:23.000 --> 18:32.000 So it's kind of a good set up, but the model gen was analog only and there was no AMS features back in the day. 18:32.000 --> 18:37.000 Model gen very log now covers most of their log A. 18:37.000 --> 18:42.000 And whatever that means really very log A is the kind of weird animal, 18:42.000 --> 18:47.000 because when some say very log A they mean spice. 18:47.000 --> 18:54.000 We mean very log A as in NXE of the LRM, which means analog stuff plus events. 18:54.000 --> 19:01.000 And the growing a very log AMS support. 19:01.000 --> 19:11.000 Yeah, it goes towards the features that that digital design has known from Icarus like delayed assignments and stuff. 19:11.000 --> 19:15.000 This is on the way and working on it. 19:15.000 --> 19:22.000 So the connectivity overhaul is already explained already. 19:22.000 --> 19:30.000 I already explained also touches the model compiler and the code generation for same pod devices and stuff. 19:30.000 --> 19:33.000 I mean same pod devices just one example. 19:33.000 --> 19:41.000 It just means you can connect whatever to whatever in a hierarchical way and get the simulation out of it. 19:41.000 --> 19:47.000 That it would that you would want to simulate. 19:47.000 --> 19:53.000 And we have been prompted to add random number generation. 19:53.000 --> 19:58.000 Oh, there's a typo. You can keep it. 19:58.000 --> 20:06.000 Random number generation is important when you do micro electronics like semiconductor devices, 20:06.000 --> 20:12.000 mismatch simulation stuff, which is something someone else wants to do. 20:12.000 --> 20:15.000 So I added random number generation first. 20:15.000 --> 20:20.000 I had to drop something else, but this is this is ready and kicking now. 20:20.000 --> 20:27.000 And the data type framework has been streamlined and extended. 20:27.000 --> 20:32.000 So we have the three very log basic data types. 20:33.000 --> 20:36.000 Real string and integer now supported. 20:36.000 --> 20:39.000 And I think they should work in all places now. 20:39.000 --> 20:41.000 You will prove me wrong if you can. 20:41.000 --> 20:45.000 And I can fix it, but that's basically there now. 20:45.000 --> 20:54.000 Strings are great if you want to describe stuff or if you want to print out messages from devices that just monitor something. 20:54.000 --> 21:01.000 And then you can say all this device has a problem or it's overheating and stuff or you can. 21:02.000 --> 21:04.000 You can use strings to select devices. 21:04.000 --> 21:11.000 If you have identifiers in devices that enable or disable features and then have a selection process. 21:11.000 --> 21:13.000 Interges are pretty clear. 21:13.000 --> 21:17.000 I mean, we need integers to do the very log 95 feature set. 21:17.000 --> 21:20.000 And the hierarchical references. 21:20.000 --> 21:23.000 That's a bit of an interesting one. 21:23.000 --> 21:41.000 And very log has a concept of peeking into other devices during expansion and elaboration to do things like global variables or process parameters and stuff. 21:41.000 --> 21:45.000 And that mechanism is dubbed hierarchical reference. 21:45.000 --> 21:48.000 And it is exactly what you would think. 21:48.000 --> 21:54.000 To something else and something else and you want to grab it and that's your oxide thickness. 21:54.000 --> 21:55.000 Whatever. 21:55.000 --> 22:13.000 And for the designer to actually specify this in a convenient place and not use some script that turns your circuit upside down in order to make all oxide thicknesses random. 22:13.000 --> 22:19.000 And we can do it in any way using the standard procedures with hierarchical references. 22:19.000 --> 22:25.000 And there's some other feature now the storage type in appearance, which is only performance related. 22:25.000 --> 22:32.000 It doesn't really add anything, but it will make larger simulations feasible. 22:32.000 --> 22:35.000 And I will get into that in a bit. 22:35.000 --> 22:37.000 The storage type. 22:37.000 --> 22:43.000 Very log AMS has variables in each device variables can be used for different things. 22:43.000 --> 22:48.000 The user doesn't need to specify so the compiler needs to make guesses. 22:48.000 --> 22:50.000 And variables can be device states. 22:50.000 --> 22:56.000 I mean, they can be in between device states like nodes and stuff, but these are explicit. 22:56.000 --> 23:00.000 The device states themselves are implicit. 23:00.000 --> 23:06.000 And the other thing is if you have two identical devices, they can share memory. 23:06.000 --> 23:11.000 If there are some constants in them that are model related. 23:11.000 --> 23:19.000 And the ones that are neither of those two types are temporary and you don't need to store them. 23:19.000 --> 23:21.000 So that also saves memory. 23:21.000 --> 23:25.000 And it all depends on the assigned use pattern of variables. 23:25.000 --> 23:33.000 If you read a variable before you actually set it, the simulator assumes that you mean the status of that variable from the previous time step. 23:33.000 --> 23:37.000 Or from the time stuff. 23:37.000 --> 23:41.000 And that assigned use pattern needs analysis. 23:41.000 --> 23:42.000 And we do this now. 23:42.000 --> 23:46.000 And there's a heuristic implemented in the model gen. 23:46.000 --> 23:50.000 And it's a heuristic because exact computation. 23:50.000 --> 23:51.000 Well, do we want that? 23:51.000 --> 23:55.000 It might be possible, but it will have a horrendous runtime. 23:55.000 --> 24:00.000 And in most cases, wild constructions are not used. 24:00.000 --> 24:02.000 We can't move me wrong. 24:02.000 --> 24:05.000 We can gradually extend this if needed. 24:05.000 --> 24:10.000 But just to get started and make everything else work. 24:10.000 --> 24:14.000 I think that's pretty pretty good already. 24:14.000 --> 24:20.000 And we need less storage in the components because of the shared storage. 24:20.000 --> 24:22.000 We don't store temperatures anymore. 24:22.000 --> 24:27.000 And we don't store all states as not. 24:27.000 --> 24:35.000 We don't store all variable values as states in each instance of every device, which obviously reduces overhead. 24:35.000 --> 24:40.000 And that's another thing we need for scaling up. 24:40.000 --> 24:42.000 And what else do I have? 24:42.000 --> 24:47.000 Yeah, the topic for is the related work. 24:47.000 --> 24:54.000 And it's really fun because people are suddenly coming and want to do stuff with new cap. 24:54.000 --> 25:03.000 And we have set up continuous integration, which I will go into in the next slide. 25:03.000 --> 25:08.000 We have this model's repo, which is kind of an old repository. 25:08.000 --> 25:21.000 It has it shows models from other projects that run with GNU cap and it shows how to how to link them together, how to load them, how it provides unit tests for them. 25:21.000 --> 25:27.000 So we actually have regression tests on models from other projects. 25:27.000 --> 25:32.000 And we do numerical cross validation. 25:32.000 --> 25:42.000 That means someone did it and that was quite fun because most of the time everything just matched what others have computed. 25:42.000 --> 25:45.000 And the one case was a bug. 25:45.000 --> 25:47.000 So we fixed one bug. 25:47.000 --> 25:56.000 And that is going to lead into another, and it's such a like project about generic test benches. 25:56.000 --> 26:06.000 So we have test benches formulated in a way that would run in different simulator environments under different conditions and with different models and whatever you want. 26:06.000 --> 26:15.000 So the generic is the idea and there's an OSDI wrapper in production, which I cannot present yet. 26:15.000 --> 26:30.000 And the IHP, the Institute for what is it high performance processing in Frankfurt, they have a chip factory, they have a PDK, they open PDK. 26:30.000 --> 26:35.000 The IHP open PDK is some low voltage stuff. 26:35.000 --> 26:43.000 They want to support GNU cap and support their PDK for using GNU cap. 26:43.000 --> 26:48.000 Which is the other point where I give some details and a bit. 26:48.000 --> 26:53.000 So the continuous integration is thanks to Eric at common caretakers. 26:53.000 --> 27:00.000 He dropped by gave this idea, he had some scripts together and this is running. 27:00.000 --> 27:04.000 So in order to grow we need a contribution process. 27:04.000 --> 27:13.000 Everyone can contribute by writing their own plugins, but if you want to submit the bug, you would expect CI or something. 27:13.000 --> 27:17.000 And there's some structural hassle. 27:17.000 --> 27:21.000 I mean we have these repositories all over the place. 27:21.000 --> 27:26.000 And we need to find the common denominator and make it work nicely. 27:26.000 --> 27:30.000 And we need you as contributors in the end. 27:30.000 --> 27:41.000 I mean you can even contribute some free resource structure ideas that would be fun to discuss this with people from other domains or just getting some insight. 27:41.000 --> 27:47.000 I mean I do this as a sideline Eric does this as a helping hand. 27:47.000 --> 27:51.000 There's lots of work to do to make this work cleanly. 27:51.000 --> 27:56.000 We are now set to do this on codebook because codebook is the only same platform these days. 27:56.000 --> 28:02.000 And we don't need code, code pilot, nonsense and stuff. 28:02.000 --> 28:06.000 And the models and validation, the models repo. 28:06.000 --> 28:14.000 We do have the old Spice 3.5 C code that runs with GNU cap and it shows how to do that. 28:14.000 --> 28:16.000 We have wrappers for this. 28:16.000 --> 28:21.000 We have all these NG Spice releases lined up in different branches. 28:21.000 --> 28:28.000 I mean the main branch only has NG Spice 17 as a golden reference and the current. 28:28.000 --> 28:39.000 And the Berkeley university has, oh that's supposed to be a capital B in Berkeley, sorry. 28:39.000 --> 28:46.000 They have released their C code for Spice models back in the days and this also runs with GNU cap. 28:46.000 --> 28:50.000 GNU cap is the only simulator that runs the code and modified by the way. 28:50.000 --> 28:54.000 And so we can run the Berkeley models and show what the results are. 28:54.000 --> 29:08.000 There's this compact modeling coalition that has raised some attention and they collect very low A models for different devices. 29:08.000 --> 29:22.000 Like PSP and there are some some other some some resistor and lots of transistor devices that make good test cases for us. 29:22.000 --> 29:25.000 And there's lots of work in progress adding them to the repository. 29:25.000 --> 29:35.000 We are currently doing trying to generalize the process and make it streamlined. 29:35.000 --> 29:44.000 In the end we want you to be able to clone the repository type make and see all the nice binaries for these. 29:44.000 --> 29:55.000 For these coalition compact model coalition plugins as well as the old Spice devices that you can all combine together in your simulation if you like that. 29:55.000 --> 30:00.000 And the regression testing has shown up to be useful. 30:00.000 --> 30:04.000 And this is everyone needs regression tests. 30:04.000 --> 30:14.000 And when we change the solvers to new stuff we also want to know that it still works with the Spice 3F5 models. 30:14.000 --> 30:19.000 So we need that to validate every single step we take. 30:19.000 --> 30:25.000 And we already found a bug in NG Spice to a model gen using this process. 30:25.000 --> 30:28.000 I mean bugs that are more than trivial. 30:28.000 --> 30:33.000 Like that's not a semicolon bug but. 30:33.000 --> 30:40.000 And if we added other devices from other from other projects we might find some others. 30:40.000 --> 30:43.000 So the cross validation is thanks to Lucas. 30:43.000 --> 30:54.000 He has got some internet funding to make nice pictures with comparison plots and numerical tolerance checks for various devices. 30:54.000 --> 31:02.000 He looked particularly into the very log A stuff because that would catch the problems we have in origin. 31:02.000 --> 31:08.000 And here you see some plots he showed me some noise analysis. 31:08.000 --> 31:15.000 And this noise is just the numerical error exponent which means low error. 31:15.000 --> 31:21.000 And here this oscillator trajectory at transient outputs. 31:21.000 --> 31:27.000 They just basically match exactly with something another simulator would give you. 31:27.000 --> 31:31.000 And I want to extend this. 31:31.000 --> 31:44.000 We want in the end we want to use very log S for these test cases because very log S allows you to visualize the circuits and allow you to not modify them for simulation. 31:44.000 --> 31:53.000 So you actually see what you get and not some weird mix of things and you don't need extra tools so you can. 31:53.000 --> 31:56.000 You can even map very log S to spice. 31:56.000 --> 32:03.000 I mean if you know how to very log has attributes you can use attributes to to attach spice meta data. 32:03.000 --> 32:08.000 And you can turn it into a spice netless to feed into NG spice. 32:08.000 --> 32:12.000 So very log S is the format that should be used for schematics. 32:12.000 --> 32:17.000 And the separate project is on the way it's not fully agreed yet. 32:17.000 --> 32:21.000 But this is something Lucas is doing. 32:21.000 --> 32:25.000 Lucas is also working on the OSDI wrapper. 32:25.000 --> 32:39.000 That's a file format or interface format from the OpenGAF project which has stopped when the author has been hired by a company. 32:39.000 --> 32:44.000 That needs it and they have really fast compilation for analog models. 32:44.000 --> 32:52.000 They were the target was the these compact models and millions of lines of code. 32:52.000 --> 32:55.000 No, thousands of lines of code of behavioural stuff. 32:55.000 --> 33:04.000 And I have a method that is much faster than what we have in terms of compilation but they only do spice. 33:05.000 --> 33:07.000 So why not also do this? 33:07.000 --> 33:09.000 And we have wrappers. 33:09.000 --> 33:11.000 We know how spice works. 33:11.000 --> 33:17.000 Lucas is getting into the meta right now and he's working on this wrapper. 33:17.000 --> 33:22.000 And that would allow you to just add another animal to the zoo. 33:22.000 --> 33:25.000 And the IHP PDK that's the stuff in Frankfurt. 33:26.000 --> 33:29.000 Christoph has picked up some stuff. 33:29.000 --> 33:40.000 Peppin has uploaded and we are collaborating to mix cell libraries and he's finding bugs. 33:40.000 --> 33:42.000 I'm adding features. 33:42.000 --> 33:44.000 It's a nice collaboration. 33:44.000 --> 33:53.000 And that will lead to official support for canoe cap in that PDK eventually. 33:53.000 --> 34:01.000 And that's basically all I have. 34:01.000 --> 34:08.000 I mean this is really testing new features and allows me to spot gaps. 34:08.000 --> 34:15.000 And he says I want this point at page in the LRM and the language reference manual and says I want this feature. 34:15.000 --> 34:18.000 And I'm on the thanks slide already. 34:18.000 --> 34:22.000 So if you want to join us or if you want to try you can get started on the weekly on the mailing list chat. 34:22.000 --> 34:27.000 And if you want to do stuff, there's funding from an internet. 34:27.000 --> 34:32.000 It might be more funding than I can use myself. 34:32.000 --> 34:36.000 And yeah, thanks for listening and thanks for coming. 34:36.000 --> 34:39.000 And do you have any questions? 34:39.000 --> 34:42.000 We really don't have time for questions. 34:42.000 --> 34:43.000 So you can. 34:43.000 --> 34:44.000 Yes. 34:44.000 --> 34:45.000 No question time is up. 34:45.000 --> 34:46.000 Yeah. 34:46.000 --> 34:48.000 So we're moving on to the next. 34:48.000 --> 34:52.000 I'm around just just feeling to meet you outside. 34:52.000 --> 34:53.000 Thank you. 34:53.000 --> 34:54.000 Thanks Felix.