WEBVTT 00:00.000 --> 00:06.000 We will be presenting the fend room, so we will be presenting the fend room, so 00:06.000 --> 00:09.000 we will be presenting the fend room, so we will be presenting the fend room, so we will 00:09.000 --> 00:12.000 be presenting the fend room, so we will be presenting the fend room, so we will be 00:12.000 --> 00:15.000 presenting the fend room, so we will be presenting the fend room, so we will be 00:15.000 --> 00:18.000 presenting the fend room, so we will be presenting the fend room, so we will be presenting the fend 00:18.000 --> 00:25.000 room, so we will be presenting the fend room, so we will be presenting the fend 00:25.000 --> 00:30.000 room, so we will be presenting the fend room, so we will be presenting the fend 00:30.000 --> 00:33.000 room, so we will be presenting the fend room, so we will be presenting the fend 00:33.000 --> 00:38.000 room, so we will be presenting the fend room, so we will be presenting the fend 00:38.000 --> 00:42.000 room, so we will be presenting the fend room, so we will be presenting the fend 00:42.000 --> 00:52.000 room, so we will be presenting the fend room, so we will be presenting the fend room, 00:52.000 --> 00:58.000 so we will be presenting the fend room, so we will be presenting the fend room, so we 00:58.000 --> 01:02.000 will be presenting the fend room, so we will be presenting the fend room, so we will 01:02.000 --> 01:06.000 be presenting the fend room, so we will be presenting the fend room, so we will be 01:07.000 --> 01:11.000 and then we will be getting into some more detail as much as possible in this short 01:11.000 --> 01:16.000 time of the three main components that we are working on here, and then we will 01:16.000 --> 01:22.000 have some outro in the end, so fend rooms is a research project funded by the 01:22.000 --> 01:26.000 German government, it is part of a wider effort to secure the technological 01:26.000 --> 01:31.000 sovereignty, the consortium working on this consists of Farouff 01:31.000 --> 01:35.000 to the government, where I am working at T. Hakurne, the vast end of the 01:35.000 --> 01:41.000 room, and the universities in FNW, we also have an industry partner, which is the 01:41.000 --> 01:47.000 Koulon chip argument, and so the basic motivation behind the project was that 01:47.000 --> 01:52.000 there are some issues with the way a proprietary FBGA designs software 01:52.000 --> 01:58.000 works nowadays, so most of you probably know from the big vendors like 01:58.000 --> 02:02.000 signings, letters, or they have their own software suite where everything is 02:02.000 --> 02:08.000 funded together, and we identified the issues several, but the main ones 02:08.000 --> 02:13.000 were for FBGA vendors, or potential vendors, the issue is that you cannot 02:13.000 --> 02:18.000 just get into the market with your FBGA, you also need to deliver a software suite, 02:18.000 --> 02:23.000 which is of course a very big hurdle, and from the user perspective, 02:23.000 --> 02:28.000 they can run into the problem that if you have designed your workflows around 02:28.000 --> 02:32.000 one vendor's software suite, you might find yourself in the difficult position 02:32.000 --> 02:38.000 if you decide to change to somebody else's device. So the idea is that by having 02:38.000 --> 02:44.000 an open source vendor independent design software, we can potentially support 02:44.000 --> 02:48.000 anyone who would like to be supported by the software, and they can also 02:48.000 --> 02:53.000 add this support themselves if they desire that, and from the user perspective 02:53.000 --> 02:58.000 again, we have the idea of one software that can be used with any device. 02:58.000 --> 03:03.000 So how that's supposed to be achieved, the first step here is to have an open source 03:03.000 --> 03:10.000 IDE that has some helpful tools, which other IDEs also have, so we're focusing on 03:10.000 --> 03:14.000 three aspects, one is the design of systems and programmable chip, 03:15.000 --> 03:20.000 the other is visualization and simulation of designs, and then also the topic of AI 03:20.000 --> 03:27.000 acceleration is relevant here, which we are exploring with a specific example. 03:27.000 --> 03:31.000 We are also pretty early on in the project, we decided to cooperate with a 03:31.000 --> 03:36.000 German startup company called OneWare, who are already working on a 03:36.000 --> 03:41.000 free open source IDE for FPGA design, which is called OneWare Studio, and we thought 03:41.000 --> 03:46.000 it was a really good fit because the general approach is based on implementing 03:46.000 --> 03:51.000 third party tools together, and so we're just creating additional tools that 03:51.000 --> 03:55.000 can be integrated into the software, and we're also working with them to 03:55.000 --> 04:01.000 implement the whole system. So now I'll be getting into the system 04:01.000 --> 04:07.000 builder, which is my primary responsibility. So the concept is pretty simple. 04:07.000 --> 04:12.000 We want a GUI-based tool that can assist in system 04:12.000 --> 04:17.000 programmable chip design, and the idea is that it is both an easy 04:17.000 --> 04:22.000 starting point for beginners, but also convenient tool for experienced users, which 04:22.000 --> 04:26.000 is not always easy to achieve, but we hope we can get there. 04:26.000 --> 04:31.000 And so the main function of this is to create what we refer to as a base 04:31.000 --> 04:37.000 policy, so the basic central piece of the SOC would be, of course, a 04:37.000 --> 04:41.000 CPU, and bus, faster, and aberration logic on all that, and maybe 04:41.000 --> 04:48.000 some simple peripherals. And what this system builder is supposed to allow you to 04:48.000 --> 04:53.000 is to on one side configure that base system, and then define the interfaces 04:53.000 --> 04:58.000 to any additional modules you have in very long. 04:58.000 --> 05:02.000 And another aspect is that we, of course, want to automate as many 05:02.000 --> 05:06.000 dam labor tasks as possible, so anything that can be easily 05:06.000 --> 05:11.000 automated, we try to do that. So how we're going to going about this is 05:11.000 --> 05:17.000 that we're basing this on the very useful open source framework for 05:17.000 --> 05:23.000 light decks, which is already very powerful tool for a system on 05:23.000 --> 05:28.000 programmable chip design. It's a Python tool kit, based around one of these 05:28.000 --> 05:34.000 more high level hardware description languages called mygen, and it also 05:34.000 --> 05:39.000 comes with a whole range of IP calls already prepared. So how we're doing this is 05:39.000 --> 05:43.000 that we have a two parts software, so we have the GUI component, which is 05:43.000 --> 05:47.000 made with the Evalonia framework in C-sharp, for integration into the 05:47.000 --> 05:52.000 one-way studio, and then we have a Python interest script interface script, which 05:52.000 --> 05:55.000 incorporates this configuration file, and then uses lightix to generate 05:55.000 --> 06:01.000 the system based on that. And as I already said, the focus right now is 06:01.000 --> 06:07.000 on interfaces between the base system and external components. So within 06:07.000 --> 06:15.000 very lot, it's all within the same IPGA, but it's separated in that way. 06:15.000 --> 06:20.000 So we also want to make as much of the lightix features available, because 06:20.000 --> 06:24.000 it's not necessarily straightforward to access everything, especially in a 06:24.000 --> 06:29.000 generic kind of fashion. And we want to keep the interface as simple as 06:29.000 --> 06:36.000 possible, so we don't confuse anyone or waste resources. So this is 06:36.000 --> 06:40.000 some screenshots of our prototype. It's very there, but once at this point, 06:40.000 --> 06:44.000 so you have basically one main configuration where you configure your 06:44.000 --> 06:50.000 system, you can choose which kind of CPU you want. You can tweak the 06:50.000 --> 06:54.000 bus system, which then actually want to use the switchbone option, 06:54.000 --> 06:59.000 there's the option to use Axi, and potentially even more 06:59.000 --> 07:04.000 standards might be integrated in the future. And then we have this 07:04.000 --> 07:08.000 other tab here called top modules, which is where you have your own 07:08.000 --> 07:11.000 very long modules. You can read in the interfaces and the 07:11.000 --> 07:16.000 parameters and all that, and then define how you want to connect everything. 07:16.000 --> 07:20.000 And what the thing also does is that it generates the top level of 07:20.000 --> 07:25.000 the very local wrapper for you. So the current status on that is that 07:25.000 --> 07:28.000 we have this first functional prototype of which I just showed some 07:28.000 --> 07:32.000 pictures, and we're working on extending and improving the 07:32.000 --> 07:36.000 functionalities. So obviously there's a lot of, this is just working 07:36.000 --> 07:43.000 progress already still. And we're trying to improve that and 07:43.000 --> 07:48.000 also enable more of the lightx functionality. And what's now a 07:48.000 --> 07:52.000 current topic is support for the open i accelerator, which will 07:52.000 --> 07:56.000 also be presented in this top later. So with that I'll give 07:56.000 --> 08:03.000 over to Sebastian, who will tell you about this thing. 08:14.000 --> 08:20.000 Great. Thank you as a friend for the brief introduction. 08:20.000 --> 08:24.000 I'm presenting, I'm with the University of Applied Science 08:24.000 --> 08:28.000 Colone and the flagship plug-in for one of the studio from us. 08:28.000 --> 08:33.000 It's the netless viewer. It shows module instances, 08:33.000 --> 08:38.000 interconnections and hierarchy of entities from your designs from 08:38.000 --> 08:45.000 VHGL or Barrylock. And it can also do a primitive visualization 08:45.000 --> 08:51.000 after the synthesis. You can see a 16 bit processor at the 08:51.000 --> 08:55.000 wide, at later, this light will be a bigger picture of it, but it's 08:55.000 --> 08:59.000 very useful for debugging or understanding from 08:59.000 --> 09:03.000 XSPCs and teaching and onboarding. Currently, we are using 09:03.000 --> 09:10.000 this tool in basic module on our university. Here is the 09:10.000 --> 09:15.000 16 bit processor. Again, a little bit bigger. We did not choose 09:15.000 --> 09:19.000 to use. It was 5-1 because Benu can't see anything. It's 09:19.000 --> 09:27.000 like a FPGA, 80% of the elements of the area, because for 09:27.000 --> 09:34.000 the routing. You can see the standard OSS of 09:34.000 --> 09:38.000 PGA to change the quality supporting in one studio or with 09:38.000 --> 09:44.000 our plug-in. The standard simulation is way to 09:44.000 --> 09:48.000 use it. It's with users or with a GL. Plug-in 09:48.000 --> 09:53.000 itself with users. And then you go from GL to GL. 09:53.000 --> 09:59.000 If you have VHGL code, you simulate the GL. And if you 09:59.000 --> 10:04.000 have Barrylock, you can simulate it with each of those 10:04.000 --> 10:09.000 very log. And show them in a way from where 10:09.000 --> 10:14.000 you are already included in one studio. And now 10:14.000 --> 10:19.000 our plug-in fills the gap where you can visualize the 10:19.000 --> 10:23.000 your design from the different steps. It's like 10:23.000 --> 10:29.000 very useful for debugging your own code. 10:29.000 --> 10:35.000 The current features that are supported is it's 10:35.000 --> 10:38.000 interactive so you can zoom in. You can zoom out. You can 10:38.000 --> 10:42.000 zoom out and collect the entities itself. So if you 10:42.000 --> 10:47.000 have a very large design, you have only the 10:47.000 --> 10:52.000 top level elements that you can see. And you can also 10:52.000 --> 10:56.000 jump back to your HDA code itself. So if you want to 10:56.000 --> 11:00.000 see where your max is implemented, you can jump back in 11:00.000 --> 11:06.000 the design code. This is only working if you use it 11:06.000 --> 11:09.360 use it as the plug-in is intended in one of the studio 11:09.360 --> 11:12.560 and currently under development is displaying 11:12.560 --> 11:15.840 the simulation result in the latest view 11:15.840 --> 11:19.640 so it can go from a simulation to the viewer itself 11:19.640 --> 11:21.360 and then jump back in your code 11:21.360 --> 11:24.640 if you want to fix some bugs or explain something. 11:26.880 --> 11:30.160 Here, a brief overview about one of the studio. 11:30.160 --> 11:34.880 Again, I've seen already mentioned open source plug-in 11:34.880 --> 11:38.080 based for FPGA and the better design. 11:38.080 --> 11:39.560 It's focused on lose integration 11:39.560 --> 11:43.000 so if you want to integrate your own tool 11:43.000 --> 11:48.800 or something else in this very good documentation 11:48.800 --> 11:51.720 not quite, but a very useful guide 11:51.720 --> 11:55.480 that you can integrate your tool in it 11:55.480 --> 11:58.640 and this unified environment for a specific design, 11:58.640 --> 12:01.520 tool to integration visualization and analysis 12:01.520 --> 12:04.000 and tool to also be used as standard low 12:04.000 --> 12:12.600 so you don't have to, you don't fix in the visual environment 12:12.600 --> 12:18.240 so you can do it like the other shell. 12:18.240 --> 12:22.840 And now we are coming to dance. 12:34.000 --> 12:36.000 Thanks a lot, sir. 12:36.000 --> 12:38.000 You can use it. 12:38.000 --> 12:40.000 I know it's very good. 12:40.000 --> 12:44.000 Well, we have now two projects I've featured about a simple problem 12:44.000 --> 12:49.000 I'll leave it 100 but easily just 100 and a half x and a half x and a half x and a half x. 12:49.000 --> 12:50.000 I'm muted. 12:50.000 --> 12:52.000 So I'm muted the bug. 12:52.000 --> 12:54.000 So, can you have muted the bug? 12:54.000 --> 12:56.000 Let's just do an example. 12:56.000 --> 12:59.000 We have more development and a half x and a half x and a half y. 12:59.000 --> 13:00.000 Networks? 13:00.000 --> 13:02.000 Because what's a prerequisite? 13:03.000 --> 13:06.000 We need a scalable open source hardware accelerator 13:06.000 --> 13:11.000 and the problem currently is there are no fully scalable open source hardware accelerators available. 13:11.000 --> 13:16.000 So, if it was like the another problem, we have to develop our own. 13:16.000 --> 13:22.000 We have given requirements and of course the support of multiple different newer network layers 13:22.000 --> 13:26.000 like convolution, dance, pooling, everything in it. 13:26.000 --> 13:30.000 And at the state of the art, we want also to support 13:30.000 --> 13:34.000 the embedded AI concept that are currently researched. 13:34.000 --> 13:39.000 So, use of sparsity, redundancy, reusability and also the SIMD flow. 13:39.000 --> 13:43.000 Single-straction multiple data in one process element. 13:43.000 --> 13:48.000 To realize the scalability, we used a higher-code structure 13:48.000 --> 13:53.000 so to you can use maximize the utilization and a higher-code buff ring. 13:53.000 --> 13:59.000 Also, we used the scalability to later on try test on a design space exploration 13:59.000 --> 14:03.000 to explore on how good is our performance by using different operators 14:03.000 --> 14:07.000 of maybe using more process elements or maybe using more RAM 14:07.000 --> 14:10.000 and then of the routing process to connect them. 14:10.000 --> 14:17.000 So, the question is, how good can we get the hardware for a given net? 14:17.000 --> 14:22.000 To visualize it a bit more, understandingly, you have a problem 14:22.000 --> 14:25.000 and for the problem, you have two versions, either you solve it 14:26.000 --> 14:30.000 or you will get it solved, like using tens of flow on an NX model 14:30.000 --> 14:32.000 from artificial intelligence. 14:32.000 --> 14:35.000 And from there, you generate a neural net. 14:35.000 --> 14:37.000 We call it just an NM. 14:37.000 --> 14:40.000 After that, we will put it in in our 14:40.000 --> 14:44.000 right-tune framework that will just try to optimize 14:44.000 --> 14:46.000 and find good parameters. 14:46.000 --> 14:49.000 If it finds a good parameter set, it will try out 14:49.000 --> 14:53.000 on the synthesis and routing and simulation by giving the synthesis and routing 14:54.000 --> 14:57.000 the hardware parameters and the simulation 14:57.000 --> 14:59.000 have the parameters and the neural network. 14:59.000 --> 15:01.000 From there, two things will be calculated. 15:01.000 --> 15:05.000 On one side, the resource usage is giving how many 15:05.000 --> 15:08.000 look-up tables do we need, how many block RAMs do we need 15:08.000 --> 15:11.000 and on the other hand, we need a time and usage of post-element 15:11.000 --> 15:18.000 so we can actually calculate what is the percentage of use hardware materials. 15:18.000 --> 15:22.000 This will iterate about multiple iterations 15:22.000 --> 15:25.000 and after that, the data is get saved and can be plotted. 15:25.000 --> 15:28.000 So if you like that interest, okay, is there maybe a peak 15:28.000 --> 15:30.000 and energy consumption somewhere? 15:30.000 --> 15:33.000 Well, it would lay the peak or is there maybe 15:33.000 --> 15:37.000 some value that you can utilize, some effects on. 15:37.000 --> 15:41.000 If we look at the open-eye-hide structure, 15:41.000 --> 15:45.000 it's mostly the structure that's given of the 15:45.000 --> 15:48.000 Iris version two model, so it's also like the 15:48.000 --> 15:51.000 stationery data flow and consists of a control 15:51.000 --> 15:53.000 logic on the top left. 15:53.000 --> 15:57.000 The parallel open-eye, which can be also used to perform 15:57.000 --> 16:01.000 in an asic implementation and some configurable RAMs 16:01.000 --> 16:04.000 that have like the current information of the whole layer 16:04.000 --> 16:06.000 start, so it can be accessed. 16:06.000 --> 16:10.000 Now another problem at the scalability is that you have 16:10.000 --> 16:12.000 if you try to scale it up, that you're routing 16:12.000 --> 16:15.000 costs increase increase increase exponentially. 16:16.000 --> 16:20.000 We solved this problem on the Iris file two version 16:20.000 --> 16:23.000 by only locally connecting each open-eye cluster 16:23.000 --> 16:28.000 to another cluster and can be variable connected up. 16:28.000 --> 16:31.000 So they can be connected and therefore the router 16:31.000 --> 16:33.000 performance increases. 16:33.000 --> 16:37.000 Looking ahead, the project is still in an early 16:37.000 --> 16:40.000 and a voting stage and we invite you all to test 16:40.000 --> 16:42.000 and challenge the software. 16:42.000 --> 16:45.000 Currently, there is an open source project and you can 16:45.000 --> 16:46.000 inspect and modify the code. 16:46.000 --> 16:48.000 You can also contribute improvements and 16:48.000 --> 16:50.000 your own ideas, or maybe your own nets, or 16:50.000 --> 16:52.000 your own features you want. 16:52.000 --> 16:56.000 Well, in this case, then join us in shaping an open 16:56.000 --> 16:58.000 vendor independent FPGA ecosystem. 16:58.000 --> 17:02.000 We are just in two slides come to the repositories. 17:02.000 --> 17:05.000 But first we have always to display that this is a 17:05.000 --> 17:06.000 Fentrums project. 17:06.000 --> 17:10.000 So we are funded by the German Federation Ministry of Research 17:10.000 --> 17:13.000 and we are currently in space, BMFTR, 17:13.000 --> 17:16.000 and this given research number if someone can now 17:16.000 --> 17:18.000 take a photo once, you can take a photo. 17:18.000 --> 17:22.000 Otherwise, we have also the project and the 17:22.000 --> 17:25.000 GitHub and we are currently now also starting on 17:25.000 --> 17:27.000 CodeBurke. 17:27.000 --> 17:30.000 So if you feel any questions, feel free to ask 17:30.000 --> 17:33.000 if you have anything you want to know. 17:34.000 --> 17:37.000 And I would like to ask about the routing 17:37.000 --> 17:40.000 complexity specifically. 17:40.000 --> 17:45.000 Is there any tools that allow me to take some of the 17:45.000 --> 17:47.000 complexity on to yourself? 17:47.000 --> 17:49.000 As in mining the rounds, the connections 17:49.000 --> 17:51.000 in various logical elements. 17:51.000 --> 17:54.000 Is there a commitment to the code itself 17:54.000 --> 17:57.000 that in the total time of the year before you? 17:57.000 --> 18:00.000 So, for my part, I just want to 18:00.000 --> 18:01.000 know that there are a lot of parts. 18:01.000 --> 18:03.000 So there is like the given complexity of that. 18:03.000 --> 18:05.000 If you mean like something like an 18:05.000 --> 18:08.000 LXP in our routing, I would give to my colleagues 18:08.000 --> 18:09.000 with question. 18:09.000 --> 18:14.000 If you feel something more like this. 18:14.000 --> 18:16.000 I don't know either. 18:16.000 --> 18:19.000 But you can place some parameters in 18:19.000 --> 18:20.000 NXP. 18:20.000 --> 18:22.000 So you have kind of handling. 18:22.000 --> 18:24.000 What's the routing? 18:25.000 --> 18:27.000 I was thinking about latency. 18:27.000 --> 18:30.000 Reviews of latency between specific logical components 18:30.000 --> 18:32.000 of the language. 18:32.000 --> 18:35.000 You. 18:35.000 --> 18:39.000 The question is about latency minimization 18:39.000 --> 18:42.000 from different components. 18:42.000 --> 18:45.000 I think you can flop land it. 18:45.000 --> 18:47.000 But you can't root yourself. 18:47.000 --> 18:50.000 You can't say which switch box you want to use 18:50.000 --> 18:53.000 or something like this. 18:53.000 --> 18:56.000 Actually, just for the case of our test study case, 18:56.000 --> 18:57.000 we had the route test. 18:57.000 --> 19:00.000 And also, we had like some delay elements in it 19:00.000 --> 19:02.000 that you can freely enable and disable. 19:02.000 --> 19:05.000 By using this elements, you can try to achieve 19:05.000 --> 19:07.000 over learning the architecture. 19:07.000 --> 19:10.000 To increase the maximum speed or maximum clock 19:10.000 --> 19:12.000 we can see if you mean something like going 19:12.000 --> 19:14.000 this on the very log face. 19:14.000 --> 19:17.000 Can you repeat the question? 19:17.000 --> 19:20.000 Can you repeat the question? 19:21.000 --> 19:23.000 Oh. 19:23.000 --> 19:26.000 Sorry. 19:26.000 --> 19:35.000 He was just asking if we can choose some integers and switch 19:35.000 --> 19:36.000 up. 19:36.000 --> 19:39.000 We have like some attributes, some defined. 19:39.000 --> 19:41.000 And we can also like have a specified defined 19:41.000 --> 19:44.000 of putting every route to stage. 19:44.000 --> 19:46.000 A separate flip flop. 19:46.000 --> 19:51.000 So it gets like one clock cycle more storaged. 19:51.000 --> 19:52.000 Yes? 19:52.000 --> 19:53.000 Yeah. 19:53.000 --> 19:54.000 So. 19:54.000 --> 19:55.000 Correct. 19:55.000 --> 19:56.000 Yeah. 19:56.000 --> 19:57.000 Put that out of the platform. 19:57.000 --> 19:59.000 We're putting all these tools together. 19:59.000 --> 20:03.000 How to split up double these your system. 20:03.000 --> 20:05.000 How to screen? 20:05.000 --> 20:09.000 So if I want to drive this externally, 20:09.000 --> 20:12.000 like by now, you visual work to help split 20:12.000 --> 20:13.000 up. 20:13.000 --> 20:19.000 It's very scripted because I'm using currently. 20:19.000 --> 20:20.000 Okay. 20:20.000 --> 20:23.000 I'm just being the question was asked. 20:23.000 --> 20:26.000 How scripted by this is from a user experience. 20:26.000 --> 20:28.000 If you want to script it without a GUI. 20:28.000 --> 20:30.000 Is it your question? 20:30.000 --> 20:34.000 So to answer this question, the part of your heart 20:34.000 --> 20:36.000 accelerator is mostly done without a GUI. 20:36.000 --> 20:41.000 So this is just you put on your very later or equals very 20:41.000 --> 20:42.000 long. 20:42.000 --> 20:45.000 And then you just put in the heart that parameters. 20:45.000 --> 20:48.000 You start it and then it generates your version of the heart 20:48.000 --> 20:50.000 accelerator for your points. 20:50.000 --> 20:55.000 Maybe you want to answer the question. 20:55.000 --> 20:59.000 It's scriptable too because we're the underlying tools. 20:59.000 --> 21:00.000 All CLI tools. 21:00.000 --> 21:05.000 So we are only building a visualization on top of the CLI tools. 21:05.000 --> 21:07.000 So you can use them if you're professional. 21:07.000 --> 21:15.000 But for educational use, it's easier to show new students in IDE instead 21:15.000 --> 21:23.000 of the heartbreak with the fashion already included. 21:23.000 --> 21:25.000 Oh, sorry. 21:25.000 --> 21:27.000 Maybe I can expand on that. 21:27.000 --> 21:34.000 I think if you're asking about the whole tool chain as a whole, 21:34.000 --> 21:36.000 is that correct? 21:36.000 --> 21:40.000 That's not really a primary target audience. 21:40.000 --> 21:42.000 So because most of these tools that we're utilizing, 21:42.000 --> 21:45.000 they already have that as was already mentioned. 21:45.000 --> 21:51.000 So we're mostly focused on the essentially quality of life 21:51.000 --> 21:56.000 for the people who have some issues with scripting everything. 21:56.000 --> 21:58.000 That's more of a purpose here. 21:58.000 --> 22:01.000 Mine was more of a certain amount of things. 22:01.000 --> 22:04.000 Like, do you get more of a problem? 22:04.000 --> 22:07.000 Do you have a lot of media interface, 22:07.000 --> 22:10.000 but do you think what's more of a challenge? 22:10.000 --> 22:11.000 Yeah. 22:11.000 --> 22:15.000 So the question was about, 22:15.000 --> 22:21.000 wait, what was the question? 22:21.000 --> 22:22.000 Yeah. 22:22.000 --> 22:27.000 It was about managing the whole tool flow as one. 22:27.000 --> 22:33.000 We haven't really spent all too much thought on that at the moment. 22:33.000 --> 22:39.000 This is certainly something we would take a look at. 22:39.000 --> 22:46.000 So maybe if you could send us some information about what you're exactly thinking about, 22:46.000 --> 22:52.000 we can certainly try to incorporate elements of that if that seems reasonable. 22:53.000 --> 22:58.000 My question is about your netless gear. 22:58.000 --> 23:01.000 That's the first one to follow up. 23:01.000 --> 23:06.000 It sounds like it's just a really only type tool right from the netless. 23:06.000 --> 23:09.000 You currently, the question is, 23:09.000 --> 23:14.000 the question is, then your netless gear is a really only tool at the moment. 23:14.000 --> 23:15.000 Is that right? 23:15.000 --> 23:20.000 The question is, the netless gear has to reach out to it. 23:20.000 --> 23:26.000 Yes, it's only, it aimed dozens of, 23:26.000 --> 23:30.000 but did you expect to be a, it's a view? 23:30.000 --> 23:36.000 This is an expectation that I have to mention here that they want to wipe that. 23:36.000 --> 23:40.000 Yes, but they request that you be able to edit from that as well, 23:40.000 --> 23:42.000 and it will put you in the there along. 23:42.000 --> 23:45.000 Maybe that's a really like question. 23:46.000 --> 23:49.000 I understand that it's not exactly right. 23:49.000 --> 23:50.000 You're all totally. 23:50.000 --> 23:56.000 But there is a art to the complexity of the top level of wire management. 23:56.000 --> 24:01.000 And we have lots of wires to see if we get this or this busted, you know? 24:01.000 --> 24:05.000 And so having a visual tool to see how that connects together in a schematic, 24:05.000 --> 24:07.000 like that goes on people a lot. 24:07.000 --> 24:10.000 So I'm wondering if you get that sort of question. 24:16.000 --> 24:23.000 The question is to make the netless gear interactive, 24:23.000 --> 24:31.000 so you can connect parts of the top level entities with a wagon drop tool. 24:31.000 --> 24:35.000 With some kind of visualization. 24:35.000 --> 24:40.000 Yeah, it's like something you can scroll around in or is it just a picture? 24:40.000 --> 24:42.000 It's something you can scroll around with, 24:42.000 --> 24:47.000 you can collapse the entities or you can hide them at all. 24:47.000 --> 24:49.000 I think you can hide them. 24:49.000 --> 24:51.000 Two bookbath. 24:51.000 --> 24:56.000 It's only visual, but he is working on something. 24:56.000 --> 24:57.000 No? 24:57.000 --> 24:58.000 Okay. 24:58.000 --> 24:59.000 Sorry. 24:59.000 --> 25:00.000 He isn't. 25:02.000 --> 25:05.000 So the answer is no one's ever requested that. 25:07.000 --> 25:11.000 Well, maybe that was what I was going to talk about. 25:11.000 --> 25:14.000 We have considered that. 25:14.000 --> 25:19.000 And we found that it's not easy to do well. 25:19.000 --> 25:24.000 So we haven't necessarily put it on the top of the priority list. 25:24.000 --> 25:28.000 So we would be happy to, at some point, get there, 25:28.000 --> 25:32.000 but it's not really something that we're prioritizing at the moment. 25:32.000 --> 25:35.000 What difficulties did you run into there? 25:35.000 --> 25:36.000 What? 25:36.000 --> 25:38.000 Can you say a part of the answers? 25:38.000 --> 25:40.000 So we have some things. 25:40.000 --> 25:44.000 For example, we have different stages in the design. 25:44.000 --> 25:45.000 Oh yeah. 25:45.000 --> 25:49.000 The question was what specific difficulties we encountered. 25:49.000 --> 25:52.000 So we have certain design stages. 25:52.000 --> 25:57.000 So for example, if you just have a very low code that you're visualizing, 25:57.000 --> 26:00.000 it's relatively straightforward to go back to the very low code. 26:00.000 --> 26:06.000 It's a bit more difficult if you have, for example, synthesized or implemented design. 26:06.000 --> 26:10.000 And you make a change there, then you also need to log that somehow. 26:10.000 --> 26:15.000 And how do you get back to reflect that in the original source? 26:15.000 --> 26:17.000 So that might be an issue. 26:17.000 --> 26:21.000 And we haven't really found a good solution that really satisfied us. 26:21.000 --> 26:24.000 And as I said, we didn't prioritize it necessarily. 26:24.000 --> 26:29.000 So if anybody has a great idea, feel free to share. 26:36.000 --> 26:49.000 So do we start from the net list or do we start from the very low? 26:49.000 --> 26:50.000 Yes. 26:50.000 --> 27:02.000 Because the net list viewer internal uses users to produce a hierarchy, the net list. 27:02.000 --> 27:06.000 And this net list, we are using for the visualization. 27:06.000 --> 27:09.000 So yes. 27:09.000 --> 27:18.000 I could plan something by any visitor or something. 27:18.000 --> 27:23.000 Some of the, some of the more complex. 27:23.000 --> 27:27.000 We have, like, a lot of stuff you think of here. 27:27.000 --> 27:34.000 And if I go ahead and stuff you have, for example, the developer and all this. 27:34.000 --> 27:37.000 Since no one wants to use by hand. 27:37.000 --> 27:40.000 And but maybe it was that much fun. 27:40.000 --> 27:46.000 Especially if you are, you know, that is something. 27:46.000 --> 27:56.000 So the question is, whether we are planning on adding some sort of IP wizard that allows configuration with a simple interface. 27:56.000 --> 27:58.000 And you're the answer is yes. 27:58.000 --> 28:06.000 We haven't gotten to that yet, but that is certainly on your agenda. 28:06.000 --> 28:10.000 You mentioned we have a lot of work on buildup. 28:10.000 --> 28:24.000 And is it somehow planned to make it possible to have design partitions and lot of these partitions and visualize a thing of different areas of the network here? 28:24.000 --> 28:36.000 The question is, it's the plan to use a floor plan visualization tool to create one. 28:36.000 --> 28:41.000 It isn't in this tool because this tool is only for the net list. 28:41.000 --> 28:46.000 And the floor planning is something you can do in the later stage. 28:46.000 --> 28:49.000 But it's an open feature. 28:49.000 --> 29:00.000 I invite you to make this purpose. 29:00.000 --> 29:08.000 So questions. 29:08.000 --> 29:10.000 Thank you very much. 29:19.000 --> 29:25.000 Thank you very much.